Epson S1C33210 - Manual (Page 458)

V DMA BLOCK: HSDMA (High-Speed DMA)
B-V-2-6 EPSON S1C33210 FUNCTION PART
Setting the Registers in Single-Address Mode
Make sure that the HSDMA channel is disabled (HSx_EN = "0") before seffing the control information.
Address mode
The address mode select bit DUALMx should be set to "0" (single-address mode). This bit is set to "0" at initial
reset.
Transfer mode
A transfer mode should be set using the DxMOD[1:0] bits.
• Single transfer mode
(DxMOD = "00", default)
• Successive transfer mode (DxMOD = "01")
• Block transfer mode
(DxMOD = "10")
Refer to the explanation in "Setting the Registers in Dual-Address Mode".
Direction of transfer
The direction of data transfer should be set using DxDIR.
D0DIR: Ch. 0 transfer direction control (DE) / HSDMA Ch. 0 control register (0x48222)
D1DIR: Ch. 1 transfer direction control (DE) / HSDMA Ch. 1 control register (0x48232)
D2DIR: Ch. 2 transfer direction control (DE) / HSDMA Ch. 2 control register (0x48242)
D3DIR: Ch. 3 transfer direction control (DE) / HSDMA Ch. 3 control register (0x48252)
Memory write operations (data transfer from I/O device to memory) are specified by writing "1" and memory
read operations (data transfer from memory to I/O device) are specified by writing "0".
Transfer data size
The DATSIZEx bit is used to set the unit size of data to be transferred.
A half-word size (16 bits) is assumed if this bit is "1" and a byte size (8 bits) is assumed if this bit is "0"
(default).
Block length
When using block transfer mode (DxMOD = "10"), the data block length (in units of DATSIZEx) should be set
using the BLKLENx[7:0] bits.
In single transfer and successive transfer modes, BLKLENx[7:0] is used as the bits7–0 of the transfer counter.
Transfer counter
Block transfer mode
In block transfer mode, up to 16 bits of transfer count can be specified using TCx_L[7:0] and TCx_H[7:0].
Single transfer and successive transfer modes
In single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using
BLKLENx[7:0], TCx_L[7:0] and TCx_H[7:0].
Memory address
In single-address mode, SxADRL[15:0] and SxADRH[11:0] are used to specify a memory address.
S0ADRL[15:0]:
Ch. 0 memory address [15:0] (D[F:0]) / Ch. 0 low-order source address set-up register (0x48224)
S0ADRH[11:0]: Ch. 0 memory address [27:16] (D[B:0]) / Ch. 0 high-order source address set-up register (0x48226)
S1ADRL[15:0]: Ch. 1 memory address [15:0] (D[F:0]) / Ch. 1 low-order source address set-up register (0x48234)
S1ADRH[11:0]: Ch. 1 memory address [27:16] (D[B:0]) / Ch. 1 high-order source address set-up register (0x48236)
S2ADRL[15:0]: Ch. 2 memory address [15:0] (D[F:0]) / Ch. 2 low-order source address set-up register (0x48244)
S2ADRH[11:0]: Ch. 2 memory address [27:16] (D[B:0]) / Ch. 2 high-order source address set-up register (0x48246)
S3ADRL[15:0]: Ch. 3 memory address [15:0] (D[F:0]) / Ch. 3 low-order source address set-up register (0x48254)
S3ADRH[11:0]: Ch. 3 memory address [27:16] (D[B:0]) / Ch. 3 high-order source address set-up register (0x48256)
In single-address mode, data transfer is performed between the memory connected to the system interface and
an external I/O device. The I/O device is accessed directly by the #DMAACKx signal, so it is unnecessary to
specify an address. DxADRL[15:0] and DxADRH[11:0] are not used in single-address mode.