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Epson S1C33210 User Manual

Page 472

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V DMA BLOCK: HSDMA (High-Speed DMA)

B-V-2-20

EPSON

S1C33210 FUNCTION PART

Name

Address

Register name

Bit

Function

Setting

Init.

R/W

Remarks

DUALM0

D0DIR

TC0_H7

TC0_H6

TC0_H5

TC0_H4

TC0_H3

TC0_H2

TC0_H1

TC0_H0

DF

DE

DD–8

D7

D6

D5

D4

D3

D2

D1

D0

Ch.0 address mode selection

D) Invalid

S) Ch.0 transfer direction control

reserved

Ch.0 transfer counter[15:8]

(block transfer mode)

Ch.0 transfer counter[23:16]

(single/successive transfer mode)

1 Dual addr

0 Single addr

1 Memory WR 0 Memory RD

0

0

X

X

X

X

X

X

X

X

R/W

R/W

R/W

Undefined in read.

0048222

(HW)

High-speed

DMA Ch.0

control register

Note:
D) Dual address

mode

S) Single

address
mode

S0ADRL15

S0ADRL14

S0ADRL13

S0ADRL12

S0ADRL11

S0ADRL10

S0ADRL9

S0ADRL8

S0ADRL7

S0ADRL6

S0ADRL5

S0ADRL4

S0ADRL3

S0ADRL2

S0ADRL1

S0ADRL0

DF

DE

DD

DC

DB

DA

D9

A8

D7

D6

D5

D4

D3

D2

D1

D0

D) Ch.0 source address[15:0]

S) Ch.0 memory address[15:0]

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

R/W

0048224

(HW)

High-speed

DMA Ch.0

low-order

source address

set-up register

Note:
D) Dual address

mode

S) Single

address
mode

DATSIZE0

S0IN1

S0IN0

S0ADRH11

S0ADRH10

S0ADRH9

S0ADRH8

S0ADRH7

S0ADRH6

S0ADRH5

S0ADRH4

S0ADRH3

S0ADRH2

S0ADRH1

S0ADRH0

DF

DE

DD

DC

DB

DA

D9

A8

D7

D6

D5

D4

D3

D2

D1

D0

reserved

Ch.0 transfer data size

D) Ch.0 source address control

S) Ch.0 memory address control

D) Ch.0 source address[27:16]

S) Ch.0 memory address[27:16]

0

0

0

X

X

X

X

X

X

X

X

X

X

X

X

R/W

R/W

R/W

0048226

(HW)

1 Half word

0 Byte

High-speed

DMA Ch.0

high-order

source address

set-up register

Note:
D) Dual address

mode

S) Single

address
mode

1

1

0

0

1

0

1

0

S0IN[1:0]

Inc/dec

Inc.(no init)

Inc.(init)

Dec.(no init)

Fixed

D0ADRL15

D0ADRL14

D0ADRL13

D0ADRL12

D0ADRL11

D0ADRL10

D0ADRL9

D0ADRL8

D0ADRL7

D0ADRL6

D0ADRL5

D0ADRL4

D0ADRL3

D0ADRL2

D0ADRL1

D0ADRL0

DF

DE

DD

DC

DB

DA

D9

A8

D7

D6

D5

D4

D3

D2

D1

D0

D) Ch.0 destination address[15:0]

S) Invalid

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

R/W

0048228

(HW)

High-speed

DMA Ch.0

low-order

destination

address set-up

register

Note:
D) Dual address

mode

S) Single

address
mode