A.4 sram (55ns), Sram interface setup examples – 55ns, Sram interface timing – 55ns – Epson S1C33210 User Manual
Page 116
APPENDIX A
A-102
EPSON
S1C33210 PRODUCT PART
A.4 SRAM (55ns)
SRAM interface setup examples – 55ns
Operating
Read cycle
Write cycle
Output disable
frequency
Wait cycle
Read cycle
delay time
20MHz
1
2
2
1.5
25MHz
2
3
3
1.5
33MHz
2
3
3
1.5
SRAM interface timing – 55ns
SRAM interface
33MHz
25MHz
20MHz
Parameter
Symbol
Min.
Max.
Cycle
Time
Cycle
Time
Cycle
Time
Read cycle time
t
RC
55
–
3
90
3
120
2
100
Address access time
t
ACC
–
55
3
90
3
120
2
100
#CE access time
t
ACS
–
55
3
90
3
120
2
100
#OE access time
t
OE
–
30
2.5
75
2.5
100
1.5
75
Output disable delay time
t
OHZ
0
30
1.5
45
1.5
60
1.5
75
Write cycle time
t
WC
55
–
3
90
3
120
2
100
Address enable time
t
AW
50
–
2.5
75
2.5
100
1.5
75
Write pulse width
t
WP
45
–
2
60
2
80
1
50
Input data setup time
t
DW
30
–
2
60
2
80
1
50
Input data hold time
t
DH
0
–
0.5
15
0.5
20
0.5
25
SRAM: 55ns, CPU: 33/25MHz, read cycle
t
RC
t
ACC
t
ACS
t
OE
BCLK
A[23:0]
#CEx
#RD
D[15:0]
RD data
;;;;;
;;;;;
;;;;;;;;;
;;;;;;;;;
;;;;
;;;;
t
OHZ
SRAM: 55ns, CPU: 33/25MHz, write cycle
t
WC
t
AW
t
WP
t
DW
BCLK
A[23:0]
#CEx
#WP
D[15:0]
WR data
;;;;;
;;;;;
;;;
;;;
t
DH