Epson S1C33210 User Manual
Page 409
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
S1C33210 FUNCTION PART
EPSON
B-III-10-23
Name
Address
Register name
Bit
Function
Setting
Init.
R/W
Remarks
–
RXINT
–
CRCER
RXBS
–
D15–8
D7
D6–3
D2
D1
D0
–
PHS receive interrupt flag
–
PHS receive data CRC-32 error flag
PHS receive buffer select
–
–
–
–
–
0
–
X
X
–
–
R/W
–
R
R
–
0 when being read.
Write "1" to clear
0 when being read.
0 when being read.
0200206
(HW)
PHS receive
status register
1 Request pending 0 No interrupts
1 CRC error
0 No error
1 Buffer B
0 Buffer A
–
ERES
RESINT
–
RRXINT
RTXINT
D15–8
D7
D6
D5–2
D1
D0
–
HDLC error reset
HDLC reset E/S INT
–
HDLC reset Rx INT
HDLC reset Tx INT
–
–
–
0
0
–
0
0
–
W
W
–
W
W
0 when being read.
0 when being read.
0200302
(HW)
1 Reset
0 Ignored
1 Reset
0 Ignored
1 Reset
0 Ignored
1 Reset
0 Ignored
HDLC interrupt
control register
–
ABRTIES
TXUEIES
HUNTIES
IDLDIES
–
D15–8
D7
D6
D5
D4
D3–0
–
HDLC enable bit for Abort
HDLC enable bit for Tx underrun/EOM
HDLC enable bit for Hunt
HDLC enable bit for idle detect
conditions
–
–
–
–
0
0
0
0
–
–
R/W
R/W
R/W
R/W
–
0 when being read.
Writes of "0" are ignored
Writes of "0" are ignored
Writes of "0" are ignored
Writes of "0" are ignored
0 when being read.
0200304
(HW)
1 Enable
0 Disabled
1 Enable
0 Disabled
1 Enable
0 Disabled
1 Enable
0 Disabled
HDLC interrupt
enable settings
register
–
ABRTIEC
TXUEIEC
HUNTIEC
IDLDIEC
–
D15–8
D7
D6
D5
D4
D3–0
–
HDLC clear enable bit for Abort
HDLC clear enable bit for Tx
underrun/EOM
HDLC clear enable bit for Hunt
HDLC clear enable bit for idle
detect conditions
–
–
–
–
0
0
0
0
–
1
1
1
1
0
0
0
0
–
R/W
R/W
R/W
R/W
–
0 when being read.
0 when being read.
0200306
(HW)
Clear interrupt
enable
Clear interrupt
enable
Clear interrupt
enable
Clear interrupt
enable
Ignored
Ignored
Ignored
Ignored
HDLC clear
interrupt
enable register
–
RXENS
TXENS
–
RXIES
TXIES
D15–8
D7
D6
D5–2
D1
D0
–
HDLC receive enable
HDLC transmit enable
–
HDLC Rx and Sp INT enable
HDLC Tx INT enable
–
–
–
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
0 when being read.
Writes of "0" are ignored
Writes of "0" are ignored
0 when being read.
Writes of "0" are ignored
Writes of "0" are ignored
0200308
(HW)
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disabled
1 Enable
0 Disabled
HDLC transfer
settings
register
–
RXENC
TXENC
–
RXIEC
TXIEC
D15–8
D7
D6
D5–2
D1
D0
–
HDLC clear receive enable
HDLC clear transmit enable
–
HDLC clear Rx and Sp INT enable
HDLC clear Tx INT enable
–
–
–
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
0 when being read.
0 when being read.
020030A
(HW)
1 Clear enable 0 Ignored
1 Clear enable 0 Ignored
1 Clear enable 0 Ignored
1 Clear enable 0 Ignored
HDLC cancel
transfer
register
–
RXADD7
RXADD6
RXADD5
RXADD4
RXADD3
RXADD2
RXADD1
RXADD0
D15–8
D7
D6
D5
D4
D3
D2
D1
D0
–
HDLC receive address
RXADD7 = MSB
RXADD0 = LSB
–
0
0
0
0
0
0
0
0
–
R/W
0 when being read.
020030C
(HW)
–
0x00 to 0xFF
HDLC receive
address
register
–
ADDCE
ADDCM
IDLDE
SHFDE
–
D15–8
D7
D6
D5
D4
D3–0
–
HDLC address compare enable
HDLC address compare mode
HDLC idle detect enable
HDLC short frame detect enable
–
–
–
–
0
0
0
0
–
–
R/W
R/W
R/W
R/W
–
0 when being read.
0 when being read.
020030E
(HW)
1 Enable
0 Disable
1 Half
0 Full
1 Enable
0 Disable
1 Enable
0 Disable
HDLC receive
operation
settings
registe
r
–
RXFTH2
RXFTH1
RXFTH0
D15–3
D2
D1
D0
–
HDLC receive queue interrupt
threshold
–
0
0
0
–
R/W
R/W
R/W
0 when being read.
0200310
(HW)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
RXFTH[2:0]
Level
8 (Full)
7
6
5
4 (Half)
3
2
1 (receive
character available)
HDLC receive
queue interrupt
threshold
register
–