Epson S1C33210 - Manual (Page 416)

III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
B-III-10-30 EPSON S1C33210 FUNCTION PART
TXINTE: PHS transmit interrupt enable (D7) / PHS transmit control register (0x0200200)
TXBS:
PHS transmit buffer select (D1) / PHS transmit control register (0x0200200)
TXEN: PHS transmit enable (D0) / PHS transmit control register (0x0200200)
These bits control PHS transmit operation. The hardware latches the register contents at the PHS transmit interrupt,
so update these bits between one such interrupt request and the next.
Setting TXINTE to "1" produces a PHS transmit interrupt every time the hardware finishes sending a 640-bit PIAFS
frame––that is, every 20 ms for 32 kbps operation and every 10 ms for 64 kbps operation.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
TXBS specifies the buffer containing the data to transmit: A ("0") or B ("1").
Write "1": B buffers at 0x0200650 to 0x020069f
Write "0": A buffers at 0x0200600 to 0x020064f
Setting TXEN to "1" starts transmission from the specified transmit buffer using the PHS clock timing.
Write "1": Transmit enabled
Write "0": Transmit disabled
TXINT: PHS transmit interrupt flag (D7) / PHS transmit status register (0x0200202)
This bit gives the status of PHS transmit operation.
The hardware updates the contents simultaneously with the PHS transmit interrupt after every 640-bit PIAFS
frame––that is, every 20 ms for 32 kbps operation and every 10 ms for 64 kbps operation.
A "1" in TXINT indicate that a PHS transmit interrupt is pending.
Read "1": PHS transmit interrupt genetated
Read "0": No interrupt genetated
Writing "1" to TXINT clears the interrupt request.
Write "1": Clear the interrupt request
Write "0": Invalid
RXINTE: PHS receive interrupt enable (D7) / PHS receive control register (0x0200204)
RXEN:
PHS receive enable (D0) / PHS receive control register (0x0200204)
These bits control PHS receive operation.
Setting RXINTE to "1" produces a PHS receive interrupt every time the hardware finishes receiving a 640-bit
PIAFS frame.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
Setting RXEN to "1" starts data storage in the currently selected receive buffer when hardware detects the FI code
and SYNC pattern.
Write "1": Receive enabled
Write "0": Receive disabled