Epson S1C33210 - Manual (Page 132)

I OUTLINE: BLOCK DIAGRAM
B-I-2-2 EPSON S1C33210 FUNCTION PART
C33 Core Block
The C33 Core Block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC
(Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface,
and an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells.
The C33 Core Block employs the S1C33000 32-bit RISC type CPU as the core CPU.
C33 Peripheral Block
The C33 Peripheral Block consists of a prescaler, six channels of 8-bit programmable timer, six channels of
16-bit programmable timer including watchdog timer and event counter functions, four channels of serial
interface, mobile access interfaces (one PHS, PDC, and HDLC channel each), input and I/O ports, and a clock
timer.
C33 Analog Block
The analog block consists of a 10-bit A/D converter with eight input channels.
C33 DMA Block
The DMA block is configured with two types of DMA controllers: HSDMA (High-Speed DMA) that has on-
chip registers for controlling DMA command information and IDMA (Intelligent DMA) that uses a memory
area for storing DMA command information.
C33 Memory Block
The following internal memory area are provided;
8 KB SRAM
For details of the blocks, refer to the respective section in this manual.