Epson S1C33210 - Manual (Page 547)

APPENDIX: I/O MAP
S1C33210 FUNCTION PART EPSON B-APPENDIX-39
Name Address Register name Bit Function Setting Init. R/W Remarks
TC2_L7
TC2_L6
TC2_L5
TC2_L4
TC2_L3
TC2_L2
TC2_L1
TC2_L0
BLKLEN27
BLKLEN26
BLKLEN25
BLKLEN24
BLKLEN23
BLKLEN22
BLKLEN21
BLKLEN20
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 transfer counter[7:0]
(block transfer mode)
Ch.2 transfer counter[15:8]
(single/successive transfer mode)
Ch.2 block length
(block transfer mode)
Ch.2 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048240
(HW)
High-speed
DMA Ch.2
transfer
counter
register
–
–
DUALM2
D2DIR
–
TC2_H7
TC2_H6
TC2_H5
TC2_H4
TC2_H3
TC2_H2
TC2_H1
TC2_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 address mode selection
D) Invalid
S) Ch.2 transfer direction control
reserved
Ch.2 transfer counter[15:8]
(block transfer mode)
Ch.2 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1 Memory WR 0 Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W
Undefined in read.
0048242
(HW)
High-speed
DMA Ch.2
control register
Note:
D) Dual address
mode
S) Single
address
mode
S2ADRL15
S2ADRL14
S2ADRL13
S2ADRL12
S2ADRL11
S2ADRL10
S2ADRL9
S2ADRL8
S2ADRL7
S2ADRL6
S2ADRL5
S2ADRL4
S2ADRL3
S2ADRL2
S2ADRL1
S2ADRL0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.2 source address[15:0]
S) Ch.2 memory address[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W 0048244
(HW)
High-speed
DMA Ch.2
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE2
S2IN1
S2IN0
S2ADRH11
S2ADRH10
S2ADRH9
S2ADRH8
S2ADRH7
S2ADRH6
S2ADRH5
S2ADRH4
S2ADRH3
S2ADRH2
S2ADRH1
S2ADRH0
DF
DE
DD
DC
DB
DA
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.2 transfer data size
D) Ch.2 source address control
S) Ch.2 memory address control
D) Ch.2 source address[27:16]
S) Ch.2 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048246
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.2
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S2IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–