Epson S1C33210 - Manual (Page 316)

III PERIPHERAL BLOCK: CLOCK TIMER
B-III-7-12 EPSON S1C33210 FUNCTION PART
Programming Notes
(1) The low-speed (OSC1) oscillation circuit, which is the clock source for the clock timer, requires a muxmum of
three seconds for its oscillation to stabilize after it is started up. Therefore, immediately after power-on, wait
until the oscillation stabilizes before starting the clock timer.
(2) At initial reset, the clock timer counter data, the setup contents of alarms, and control bits, including
RUN/STOP, are not initialized. Therefore, always initialize the clock timer in the software following power-
on.
(3) The clock timer reset bit TCRST and the clock timer RUN/STOP control bit TCRUN are located at the same
address (0x40151). However, the clock timer cannot be reset at the same time it is set to RUN by writing "1"
to both. In this case, the reset input is ignored and the timer starts counting up from the counter values then in
effect. When resetting the timer, always make sure TCRUN = "0" (timer stopped).
(4) When the counters are cleared as the clock timer is reset, an interrupt may be generated depending on the
register settings. Therefore, before resetting the clock timer, first disable the clock timer interrupt and, after
resetting the clock timer, reset the interrupt factor flag and the interrupt factor generation and alarm factor
generation flags.
(5) To prevent generation of an unwanted interrupt, disable the clock timer interrupt before selecting the interrupt
and alarm factors. Then, before reenabling the interrupt, reset each factor generation flag and the interrupt
factor flag.
(6) The interrupt factor flag (FCTM) becomes indeterminate at initial reset. To prevent generation of an unwanted
interrupt, be sure to reset the flag in a program.
(7) To prevent regeneration of interrupts with the same factor after an interrupt has occurred, be sure to reset the
interrupt factor flag (FCTM) before setting the PSR again or executing the reti instruction.