Epson S1C33210 - Manual (Page 415)

III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
S1C33210 FUNCTION PART EPSON B-III-10-29
INTE: PDC interrupt enable (D1) / PDC interrupt register (0x0200100)
PDCINT: PDC interrupt flag(D0) / PDC interrupt register (0x0200100)
These bits respectively control and indicate the PDC interrupt requests to the CPU every 20 ms at the falling edge of
the frame signal from the PDC device.
Setting INTE to "1" enables these interrupts that generate every 20 ms at the falling edge of the frame signal from the
PDC device.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
A "1" in PDCINT indicate that one of these interrupts is pending.
Read "1": PDC interrupt genetated
Read "0": No interrupt genetated
Writing "1" to PDCINT clears the interrupt request.
Write "1": Clear the interrupt request
Write "0": Invalid
TXBS : PDC transmit buffer select (D2) / PDC command register (0x0200102)
TXEN : PDC transmit enable (D1) / PDC command register (0x0200102)
RXEN : PDC receive enable (D0) / PDC command register (0x0200102)
These bits control PDC communications. The hardware latches the register contents at the rising edges in the PDC
frame signal, so update these bits between the PDC interrupt indicating a falling edge and the next rising edge.
TXBS specifies the buffer containing the data to transmit: A ("0") or B ("1").
Write "1": B buffers at 0x0200440 to 0x0200477
Write "0": A buffers at 0x0200400 to 0x0200437
Setting TXEN to "1" starts transmission from the specified buffer at the next falling edge in the PDC frame signal.
Write "1": Transmit enabled
Write "0": Transmit disabled
Setting RXEN to "1" starts data storage in the currently selected receive buffer at the next rising edge in the PDC
frame signal.
Write "1": Receive enabled
Write "0": Receive disabled
CRCER1: PDC receive data CRC-16 error flag (D7) / PDC status register (0x0200104)
CRCER2: PDC receive data CRC-CCITT error flag (D6) / PDC status register (0x0200104)
RXBB, RXBA: PDC receive data buffer indicators (D[1:0]) / PDC status register (0x0200104)
These bits indicate the status of PDC receive operation. The hardware updates them at the falling edges in the PDC
frame signal, simultaneous with the PDC interrupt request, so read the register contents just after the interrupt.
A "1" in CRCER1 indicates failure of the CRC-16 check.
Read "1": An error occurred
Read "0": No error occurred
A "1" in CRCER2 indicates failure of the CRC-CCITT check.
Read "1": An error occurred
Read "0": No error occurred
RXBB and RXBA indicate the buffer holding the data for the last receive operation completed. During normal,
continuous operation, the "1" alternates between the two.
Read "1": The buffer holds the data
Read "0": The buffer holds no data