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Epson S1C33210 User Manual

Page 517

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APPENDIX: I/O MAP

S1C33210 FUNCTION PART

EPSON

B-APPENDIX-9

Name

Address

Register name

Bit

Function

Setting

Init.

R/W

Remarks

0x0 to 0xFF(0x7F)

TXD07

TXD06

TXD05

TXD04

TXD03

TXD02

TXD01

TXD00

D7

D6

D5

D4

D3

D2

D1

D0

Serial I/F Ch.0 transmit data

TXD07(06) = MSB

TXD00 = LSB

X

X

X

X

X

X

X

X

R/W 7-bit asynchronous

mode does not use

TXD07.

00401E0

(B)

Serial I/F Ch.0

transmit data

register

0x0 to 0xFF(0x7F)

RXD07

RXD06

RXD05

RXD04

RXD03

RXD02

RXD01

RXD00

D7

D6

D5

D4

D3

D2

D1

D0

Serial I/F Ch.0 receive data

RXD07(06) = MSB

RXD00 = LSB

X

X

X

X

X

X

X

X

R

7-bit asynchronous

mode does not use

RXD07 (fixed at 0).

00401E1

(B)

Serial I/F Ch.0

receive data

register

TEND0

FER0

PER0

OER0

TDBE0

RDBF0

D7–6

D5

D4

D3

D2

D1

D0

Ch.0 transmit-completion flag

Ch.0 flaming error flag

Ch.0 parity error flag

Ch.0 overrun error flag

Ch.0 transmit data buffer empty

Ch.0 receive data buffer full

0

0

0

0

1

0

R

R/W

R/W

R/W

R

R

0 when being read.

Reset by writing 0.

Reset by writing 0.

Reset by writing 0.

00401E2

(B)

1 Error

0 Normal

1 Transmitting 0 End

1 Error

0 Normal

1 Error

0 Normal

1 Empty

0 Buffer full

1 Buffer full

0 Empty

Serial I/F Ch.0

status register

TXEN0

RXEN0

EPR0

PMD0

STPB0

SSCK0

SMD01

SMD00

D7

D6

D5

D4

D3

D2

D1

D0

Ch.0 transmit enable

Ch.0 receive enable

Ch.0 parity enable

Ch.0 parity mode selection

Ch.0 stop bit selection

Ch.0 input clock selection

Ch.0 transfer mode selection

1

1

0

0

1

0

1

0

SMD0[1:0]

Transfer mode

8-bit asynchronous

7-bit asynchronous

Clock sync. Slave

Clock sync. Master

0

0

X

X

X

X

X

X

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Valid only in

asynchronous mode.

00401E3

(B)

1 Enabled

0 Disabled

1 Enabled

0 Disabled

1 With parity

0 No parity

1 Odd

0 Even

1 2 bits

0 1 bit

1 #SCLK0

0 Internal clock

Serial I/F Ch.0

control register

DIVMD0

IRTL0

IRRL0

IRMD01

IRMD00

D7–5

D4

D3

D2

D1

D0

Ch.0 async. clock division ratio

Ch.0 IrDA I/F output logic inversion

Ch.0 IrDA I/F input logic inversion

Ch.0 interface mode selection

1

1

0

0

1

0

1

0

IRMD0[1:0]

I/F mode

reserved

IrDA 1.0

reserved

General I/F

X

X

X

X

X

R/W

R/W

R/W

R/W

0 when being read.

Valid only in

asynchronous mode.

00401E4

(B)

1 1/8

0 1/16

1 Inverted

0 Direct

1 Inverted

0 Direct

Serial I/F Ch.0

IrDA register