Maxim Integrated DS4830 Optical Microcontroller User Manual
Ds4830 optical microcontroller user’s guide
Table of contents
Document Outline
- SECTION 1 – OVERVIEW
- SECTION 2 – ARCHITECTURE
- SECTION 3 – SYSTEM REGISTER DESCRIPTIONS
- SECTION 4 – PERIPHERAL REGISTER DESCRIPTIONS
- SECTION 5 – INTERRUPTS
- SECTION 6 – DIGITAL-TO-ANALOG CONVERTER (DAC)
- SECTION 7 – ANALOG-TO-DIGITAL CONVERTER (ADC)
- SECTION 8 – SAMPLE AND HOLD
- SECTION 9 – QUICK TRIP (FAST COMPARATOR)
- SECTION 10 – I2C-COMPATIBLE MASTER INTERFACE
- 10.1 – Detailed Description
- 10.1.1 – Description of Master I2C Interface
- 10.1.2 – Default Operation
- 10.1.3 – I2C Clock Generation
- 10.1.4 – Timeout
- 10.1.5 – Generating a START
- 10.1.6 – Generating a STOP
- 10.1.7 – Transmitting a Slave Address
- 10.1.8 – Transmitting Data
- 10.1.9 – Receiving Data
- 10.1.10 – I2C Master Clock Stretching
- 10.1.11 – Resetting the I2C Master Controller
- 10.1.12 – Operation as a Slave
- 10.1.13 – GPIO
- 10.2 – I2C Master Controller Register Description
- 10.1 – Detailed Description
- SECTION 11 – I2C-COMPATIBLE SLAVE INTERFACE
- 11.1 – Detailed Description
- 11.1.1 – Default Operation
- 11.1.2 – Slave Address
- 11.1.3 – I2C Start Detection
- 11.1.4 – I2C Stop Detection
- 11.1.5 – Slave Address Matching
- 11.1.6 – Transmitting Data
- 11.1.7 – Receiving Data
- 11.1.8 – Clock Stretching
- 11.1.9 – SMBus Timeout
- 11.1.10 – Resetting the I2C Slave Controller
- 11.1.11 – Operation as a Master
- 11.2 – I2C Slave Controller Register Description
- 11.1 – Detailed Description
- SECTION 12 – SERIAL PERIPHERAL INTERFACE (SPI)
- 12.1 – Serial Peripheral Interface (SPI) Detailed Description
- 12.1.1 – SPI Transfer Formats
- 12.1.2 – SPI Character Lengths
- 12.2 – SPI System Errors
- 12.2.1 – Mode Fault
- 12.2.2 – Receive Overrun
- 12.2.3 – Write Collision While Busy
- 12.3 – SPI Interrupts
- 12.4 – SPI Master
- 12.4.1 – SPI Transfer Baud Rates
- 12.4.2 – SPI Master Operation
- 12.4.3 – SPI Master Register Descriptions
- 12.5 – SPI Slave
- 12.5.1 – SPI Slave Select
- 12.5.2 – SPI Transfer Baud Rates
- 12.5.3 – SPI Slave Operation
- 12.5.4 – SPI Slave Register Descriptions
- SECTION 13 – 3-WIRE
- SECTION 14 – PWM
- SECTION 15 – GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PINS
- 15.1 – Overview
- 15.2 – GPIO Port 0 Register Descriptions
- 15.2.1 – GPIO Direction Register Port 0 (PD0)
- 15.2.2 – GPIO Output Register Port 0 (PO0)
- 15.2.3 – GPIO Input Register for Port 0 (PI0)
- 15.2.4 – GPIO Port 0 External Interrupt Edge Select Register (EIES0)
- 15.2.5 – GPIO Port 0 External Interrupt Flag Register (EIF0)
- 15.2.6 – GPIO Port 0 External Interrupt Enable Register (EIE0)
- 15.3 – GPIO Port 1 Register Descriptions
- 15.3.1 – GPIO Direction Register Port 1 (PD1)
- 15.3.2 – GPIO Output Register Port 1 (PO1)
- 15.3.3 – GPIO Input Register for Port 1 (PI1)
- 15.3.4 – GPIO Port 1 External Interrupt Edge Select Register (EIES1)
- 15.3.5 – GPIO Port 1 External Interrupt Flag Register (EIF1)
- 15.3.6 – GPIO Port 1 External Interrupt Enable Register (EIE1)
- 15.4 – GPIO Port 2 Register Descriptions
- 15.4.1 – GPIO Direction Register Port 2 (PD2)
- 15.4.2 – GPIO Output Register Port 2 (PO2)
- 15.4.3 – GPIO Input Register for Port 2 (PI2)
- 15.4.4 – GPIO Port 2 External Interrupt Edge Select Register (EIES2)
- 15.4.5 – GPIO Port 2 External Interrupt Flag Register (EIF2)
- 15.4.6 – GPIO Port 2 External Interrupt Enable Register (EIE2)
- 15.5 – GPIO Port 6 Register Descriptions
- 15.5.1 – GPIO Direction Register Port 6 (PD6)
- 15.5.2 – GPIO Output Register Port 6 (PO6)
- 15.5.3 – GPIO Input Register for Port 6 (PI6)
- 15.5.4 – GPIO Port 6 External Interrupt Edge Select Register (EIES6)
- 15.5.5 – GPIO Port 6 External Interrupt Flag Register (EIF6)
- 15.5.6 – GPIO Port 6 External Interrupt Enable Register (EIE6)
- SECTION 16 – GENERAL-PURPOSE TIMERS
- SECTION 17 – SUPPLY VOLTAGE MONITOR (SVM)
- SECTION 18 – HARDWARE MULTIPLIER MODULE
- SECTION 19 – WATCHDOG TIMER
- SECTION 20 – TEST ACCESS PORT (TAP)
- SECTION 21 – IN-CIRCUIT DEBUG MODE
- SECTION 22 – IN-SYSTEM PROGRAMMING
- 22.1 – Detailed Description
- 22.2 – Bootloader Operation
- 22.3 – Bootloader Commands
- 22.3.1 - Command 00h – No Operation
- 22.3.2 - Command 01h – Exit Loader
- 22.3.3 - Command 02h – Master Erase
- 22.3.4 - Command 03h – Password Match
- 22.3.5 - Command 04h – Get Status
- 22.3.6 - Command 05h – Get Supported Commands
- 22.3.7 - Command 06h – Get Code Size
- 22.3.8 - Command 07h – Get Data Size
- 22.3.9 - Command 08h – Get Loader Version
- 22.3.10 - Command 09h – Get Utility ROM Version
- 22.3.11 - Command 10h – Load Code
- 22.3.12 - Command 11h – Load Data
- 22.3.13 - Command 20h – Dump Code
- 22.3.14 - Command 21h – Dump Data
- 22.3.15 - Command 30h – CRC Code
- 22.3.16 - Command 31h – CRC Data
- 22.3.17 - Command 40h – Verify Code
- 22.3.18 - Command 41h – Verify Data
- 22.3.19 - Command 50h – Load and Verify Code
- 22.3.20 - Command 51h – Load and Verify Data
- 22.3.21 - Command E0h – Code Page Erase
- SECTION 23 – PROGRAMMING
- 23.1 – Addressing Modes
- 23.2 – Prefixing Operations
- 23.3 – Reading and Writing Registers
- 23.4 – Reading and Writing Register Bits
- 23.5 – Using the Arithmetic and Logic Unit
- 23.5.1 – Selecting the active accumulator
- 23.5.2 – Enabling auto-increment and auto-decrement
- 23.5.3 – ALU operations using the active accumulator and a source
- 23.5.4 – ALU operations using only the active accumulator
- 23.5.5 – ALU bit operations using only the active accumulator
- 23.5.6 – Example: Adding two four-byte numbers using auto-increment
- 23.6 - Processor Status Flag Operations
- 23.7 - Controlling Program Flow
- 23.8 - Handling Interrupts
- 23.9 - Accessing the Stack
- 23.10 - Accessing Data Memory
- SECTION 24 – INSTRUCTION SET
- SECTION 25 – UTILITY ROM