Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 90)

DS4830 User’s Guide
90
11.1 – Detailed Description
11.1.1
– Default Operation
The I
2
C slave controller is enabled (I2CCN_S.I2CEN=1) by default. As long as the I
2
C slave controller is enabled, the
DS4830 I
2
C bootloader can operate. This allows bootloading of blank devices without any setup of the I
2
C slave
controller. Prior to the I
2
C slave controller being used for normal data communication, some software setup will be
required. This setup will include setting an I
2
C slave address and telling the slave controller which I
2
C events should
generate interrupts.
11.1.2
– Slave Address
Prior to communication, an I
2
C slave address may need to be selected. The I
2
C slave controller normally responds to two
slave addresses. The I
2
C bootloader uses address 34h. This bootloader address cannot be changed and should not be
used as the device slave address for normal communication. The second slave address is the address used for
communication with the host. This slave address is set using the I2CSLA_S register. The address contained in the
I2CSLA_S register is the address with the R/W bit. If an address other than 36h is desired, the I2CSLA_S register can be
programmed with this new address. The I
2
C slave controller can also be programmed to respond to a third address, the
General Call Address, which is 00h. This feature can be enabled by setting the I2CCN_S.I2CGCEN bit to a 1.
11.1.3
– I2C Start Detection
The I
2
C Slave Controller always monitors the I
2
C bus for an I
2
C start, which is a high to low transition on SDA while SCL is
held high. If an I
2
C start (or restart) condition is detected, the I
2
C slave will set the I2CSRI bit in the I2CST_S register,
which can cause an interrupt if enabled. The detection of a start brings the I
2
C controller out of its idle state. Following a
start, the I
2
C controller begins to monitor data on the I
2
C bus and the I2CBUSY bit will be set to a 1. The I2CBUS bit will
also be set to a one to indicate that the I
2
C bus is currently busy.
11.1.4
– I2C Stop Detection
The I
2
C Slave Controller also always monitors the I
2
C bus for an I
2
C stop, which is a low to high transition on SDA while
SCL is held high. If an I
2
C stop condition is detected, the I
2
C slave controller will set the I2CSPI bit in the I2CST_S
register, which can cause an interrupt if enabled. The I2CBUS bit will be cleared to 0 following a stop to indicate that the
I2C bus is no longer busy.
11.1.5
– Slave Address Matching
Following an I
2
C start or restart, the I
2
C slave controller knows that the next byte of data transmit by the host should be
the slave address. The I
2
C slave automatically monitors for the slave address without any software interaction required.
The I
2
C slave controller compares the first 7 bits received to the slave address programmed into I2CSLA_S.
After receiving the first 8 bits of data following a start, the I
2
C controller compares the first 7 bits to the value programmed
into the I2CSLA_S register. If the received slave address matches I2CSLA_S, the I
2
C slave controller does the following
steps. This is illustrated in Figure 11-2.

Transmit an ACK or NACK on the 9
th
clock based upon the setting of the I2CCN_S.I2CACK bit.

Set the I I2CSLA _S_I2CMODE bit with the value of the received R/W bit. This bit can be used by software to
determine if the I
2
C slave controller will be asked to receive or transmit data.

Set the I2CST_S.I2CAMI bit to indicate that a slave address match was made. The setting of this bit can
generate an interrupt if enabled.

Clears the I2CBUSY flag.
Upon completion of the slave data byte (7 bits of slave address + R/W bit + ACK/NACK), the I
2
C slave controller will enter
one of three states.

Data Transmit: The slave address matched and the R/W bit was a 1. The host is now expecting to clock data from
the DS4830. The DS4830 retains control of the SDA line so data can be transmitted to the host.

Data Receive: The slave address matched and the R/W bit was a 0. The host wants to write data to the DS4830.
After the ACK/NACK bit, the DS4830 releases SDA and prepares to receive a byte of data.

Wait for Start/Stop: The received slave address did not match I2CSLA_S. The controller enters idle state and
waits for the next start condition or stop condition.