Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 20)

DS4830 User’s Guide
20
2.5
– Data Alignment
To support merged program and data memory operation while maintaining efficient memory space usage, the data
memory must be able to support both byte and word mode accessing. Data is aligned in data memory as words, but the
effective data address is resolved to bytes. This data alignment allows program instruction fetching in words while
maintaining data accessibility at the byte level. It is important to realize that this accessibility requires strict word
alignment. All executable or data words must align to an even address in byte mode. Care must be taken when updating
a code segment as misalignment of words will likely result in loss of program execution control.
Memory will always be read as a complete word, whether for program fetch or data access. The program decoder always
uses a full 16-bit word. The data access can utilize a word or an individual byte. Data memory is organized as two byte-
wide memory banks with common word address decode but two 8-bit data buses. In byte mode, data pointer hardware
reads out the full word containing the selected byte using the effective data word address pointer (the least significant bit
of the byte data pointer is not initially used). Then, the least significant data pointer bit functions as the byte select that is
used to place the correct byte on the data bus. For write access, data pointer hardware addresses a particular word using
the effective data word address while the least significant bit selects the corresponding data bank for write. The contents
of the other byte are left unaffected.
2.6
– Reset Conditions
The DS4830 has several possible sources of reset.

Power-On/Brownout Reset

Watchdog Timer Reset

External Reset

Internal System Reset
Once a reset condition has completed or been removed, code execution begins at the beginning of utility ROM, which is
address 8000h. The utility ROM code interrogates the I2C_SPE, JTAG_SPE, and PWL bits to determine if bootloading is
necessary. If bootloading is not required, execution will jump to the user code reset vector, which is at flash memory
address 0000h.
The /RST\ pin is an output as well as an input. If a reset condition is generated by one of the DS4830
’s internal reset
sources (brownout, watchdog timer, or internal reset), an output reset pulse is generated on the /RST\ pin while the
DS4830 remains in reset.
2.6.1
– Power-On/Brownout Reset
The DS4830 provides a power-on reset (POR) circuit to ensure proper initialization of internal device states and analog
circuits. The POR voltage threshold range is between approximately 1.1V and 1.7V. When V
DD
is below the POR level,
the state of all the DS4830 pins, including /RST\, is weak pull up.
The DS4830 also includes brownout detection capability. This is an on-chip precision reference and comparator that
monitors the supply voltage, V
DD
, to ensure that it is within acceptable limits. If V
DD
is below the brownout level (V
BO
), the
power monitor generates a reset. This can occur when:

The DS4830 is being powered up and V
DD
is above the POR level but still less than V
BO
.

V
DD
drops from an acceptable level to less than V
BO
.
Once V
DD
exceeds V
BO
, the DS4830 exits the reset condition and the internal oscillator starts up. After approximately 1ms
(t
SU:MOSC
) the DS4830 performs the following tasks.

All registers and circuits enter their reset state

The POR flag in the Watchdog Control Register is set to indicate the source of the reset

The DS4830 begins normal operation (CPU State)

Code execution begins at utility ROM location 8000h
The transition between POR, Brownout, and normal operation is detailed in Figure 2-6: DS4830 State Diagram.
Note: If V
DD
is below V
BO
, there is a chance that the SRAM was corrupted. If the POR flag in WDCN is set, all data in
SRAM should be re-initialized.