Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 122)

DS4830 User’s Guide
122
14.3.2.1
– Local Register DCYCn
PWMCN REG_SEL = 00b
PWMDATA[15:0]  DCYCn[15:0]
BIT NAME DESCRIPTION
15:12 Reserved Reserved. The user should write 0 to these bits. These bits are ignored by the PWM
controller.
11:0 DCYCn[11:0] Duty Cycle Register. When REG_SEL[1:0] in the PWMCN SFR is set to 00b, the
PWMDATA register points to the Duty Cycle Register of the PWM channel selected by
PWM_SEL[3:0] bits in the PWMCN register. The number of bits used to program the Duty
Cycle depends on the resolution programmed in the PWMCFG register. For 12 bits of
resolution, the Duty cycle is the lower 12 bits of the PWMDATA register. However if only 7
bits of resolution is selected, only the lower 7 bits are used.
Example: if PWM_SEL[3:0] = 0101b and REG_SEL[1:0] = 00b, then the PWMDATA
register points to the Duty Cycle Register of the PWM Channel 5. A read or write to/from
PWMDATA register will read or write from the Duty Cycle Register of PWM Channel 5. If
the resolution of channel 5 is set to 9 bits, only DCYCn[8:0] will be used for programming
the Duty Cycle.