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DS4830 User’s Guide
2
Contents
SECTION 1
– OVERVIEW ...................................................................................................................................................... 9
SECTION 2
– ARCHITECTURE ........................................................................................................................................... 11
2.1
– Instruction Decoding ................................................................................................................................................. 11
2.2
– Register Space ......................................................................................................................................................... 12
2.3
– Memory Types .......................................................................................................................................................... 13
2.3.1
– Flash Memory .................................................................................................................................................... 13
2.3.2
– SRAM Memory ................................................................................................................................................... 13
2.3.3
– Utility ROM ......................................................................................................................................................... 13
2.3.4
– Stack Memory .................................................................................................................................................... 13
2.4
– Program and Data Memory Mapping and Access ................................................................................................... 14
2.4.1
– Program Memory Access .................................................................................................................................. 14
2.4.2
– Program Memory Mapping ................................................................................................................................ 15
2.4.3
– Data Memory Access ......................................................................................................................................... 15
2.4.4
– Data Memory Mapping ...................................................................................................................................... 16
2.5
– Data Alignment ......................................................................................................................................................... 20
2.6
– Reset Conditions ...................................................................................................................................................... 20
2.6.1
– Power-On/Brownout Reset ................................................................................................................................ 20
2.6.2
– Watchdog Timer Reset ...................................................................................................................................... 21
2.6.3
– External Reset ................................................................................................................................................... 21
2.6.4
– Internal System Resets ...................................................................................................................................... 22
2.7
– Clock Generation ...................................................................................................................................................... 22
SECTION 3
– SYSTEM REGISTER DESCRIPTIONS ......................................................................................................... 23
SECTION 4
– PERIPHERAL REGISTER DESCRIPTIONS ................................................................................................. 31
SECTION 5
– INTERRUPTS ................................................................................................................................................ 36
5.1
– Servicing Interrupts ................................................................................................................................................... 37
5.2
– Module Interrupt Identification Registers .................................................................................................................. 39
5.3
– Interrupt System Operation ...................................................................................................................................... 40
5.3.1
– Synchronous vs. Asynchronous Interrupt Sources ............................................................................................ 40
5.3.2
– Interrupt Prioritization by Software ..................................................................................................................... 40
5.3.3
– Interrupt Exception Window ............................................................................................................................... 40
SECTION 6
– DIGITAL-TO-ANALOG CONVERTER (DAC) ................................................................................................ 42
6.1
– Detailed Description ................................................................................................................................................. 42
6.1.1
– Reference Selection.......................................................................................................................................... 43
6.1.2
– Requirement for Enabled DACs ....................................................................................................................... 43
6.2
– DAC Register Descriptions ....................................................................................................................................... 43
6.3
–DAC Code Examples ................................................................................................................................................. 45
SECTION 7
– ANALOG-TO-DIGITAL CONVERTER (ADC) ................................................................................................ 46
7.1
– Detailed Description ................................................................................................................................................. 46
7.1.1
– ADC Controller ................................................................................................................................................... 46
7.1.2
– ADC Conversion Sequencing ............................................................................................................................ 47
