Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 96)

DS4830 User’s Guide
96
11.2.2 – I 2
C Slave Status Register (I2CST_S)
Address: M2[01h]
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name I2CBUS I2CBUSY - - I2CSPI I2CSCL I2CROI I2CGCI I2CNACKI - I2CAMI I2CTOI I2CSTRI I2CRXI I2CTXI I2CSRI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access r* r* r r rw r* rw rw rw* r rw rw rw* rw* rw rw
* Set by hardware only.
BIT NAME DESCRIPTION
15 I2CBUS I
2
C Slave Bus Busy. This bit is set to ‘1’ when a START/repeated START condition is detected and cleared
to '0' when the STOP condition is detected. This bit is reset to ‘0’ on all forms of reset or when I2CEN=0.
This bit is controlled by hardware and is read only.
14 I2CBUSY I
2
C Slave Busy. This bit is used to indicate the current status of the I
2
C module. The I2CBUSY is set to '1'
when the I
2
C controller is actively participating in a transaction. This bit is controlled by hardware and is read
only.
13:12 Reserved Reserved. The user should write 0 to these bits.
11 I2CSPI I
2
C Slave STOP Interrupt Flag. This bit is set to '1' when a STOP condition is detected. This bit must be
cleared to '0' by software once set. Setting this bit to '1' by software will cause an interrupt if enabled.
10 I2CSCL I
2
C Slave SCL Status. This bit reflects the logic state of SCL signal. This bit is set to '1' when SCL is at a
logic high (1), and cleared to '0' when SCL is at a logic low (0). This bit is controlled by hardware and is read
only.
9 I2CROI I 2 C Slave Receiver Overrun Flag. This bit indicates a receive overrun when set to '1'. This bit is set to ‘1’ if
the receiver has received two bytes since the last CPU read of I2CBUF_S. This bit can only be cleared to '0'
by software reading the I2CBUF_S. Setting this bit to 1 by software will cause an interrupt if enabled.
8 I2CGCI I
2
C Slave General Call Interrupt Flag. This bit is set to '1' when the general call is enabled (I2CGCEN=1)
and the general call address (00h) is received. This bit must be cleared to '0' by software once set. Setting
this bit to '1' by software will cause an interrupt if enabled.
7 I2CNACKI I
2 C Slave NACK Interrupt Flag. This bit is set by hardware to either a ‘1’ if a NACK was received from the
host or a ‘0’ if an ACK was received from the host. The setting of this bit to a ‘1’ will cause an interrupt if
enabled. This bit can be cleared to ‘0’ by software once set.
6 - Reserved. The user should write 0 to this bit.
5 I2CAMI I 2 C Slave Address Match Interrupt Flag. This bit is set to '1' when the I 2 C controller receives an address
that matches the contents of the slave address register (I2CSLA_S). This bit must be cleared to '0' by
software once set. Setting this bit to
‘1’ by software will cause an interrupt if enabled.
4 I2CTOI I 2 C Slave Timeout Interrupt Flag. This bit is set to ‘1’ if SMBUS timeout is enabled and SCL is low longer
than 30ms. This bit must be cleared to ‘0’ by software once set. Setting this to ’1’ will cause an interrupt if
enabled.
3 I2CSTRI I
2
C Slave Clock Stretch Interrupt Flag. This bit indicates that the I
2
C slave controller is operating with
clock stretching enabled and is currently holding the SCL clock signal low. The I
2
C controller will release
SCL after this bit has been cleared to '0'. This bit must be cleared to '0' by software once set. This bit is set
by hardware only.
2 I2CRXI I
2
C Slave Receive Ready Interrupt Flag. This bit indicates that a data byte has been received in the I
2
C
buffer. This bit must be cleared by software once set. This bit is set by hardware only.
1 I2CTXI I
2
C Slave Transmit Complete Interrupt Flag. This bit indicates that an address or a data byte has been
successfully shifted out and the I
2
C controller has received an acknowledgment from the receiver (NACK or
ACK). This bit must be cleared by software once set. Setting this bit to ‘1’ by software will cause an interrupt
if enabled.
0 I2CSRI I 2 C Slave START Interrupt Flag. This bit is set to '1' when a START condition (or restart) is detected. This
bit must be cleared to '0' by software once set. Setting this bit to '1' by software will cause an interrupt if
enabled.