Ds4830 user’s guide, 3 – breakpoint 2 register (bp2) – Maxim Integrated DS4830 Optical Microcontroller User Manual
Page 158
DS4830 User’s Guide
158
21.1.1.1
– Breakpoint 0 Register (BP0)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
BP0.15
BP0.14
BP0.13
BP0.12
BP0.11
BP0.10
BP0.9
BP0.8
BP0.7
BP0.6
BP0.5
BP0.4
BP0.3
BP0.2
BP0.1
BP0.0
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Access
s
s
s
s
S
s
s
s
s
s
s
s
s
s
s
s
s = special
The Breakpoint 0 register is accessible only via background mode read/write commands. Breakpoint registers BP0, BP1,
BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the debug
engine monitors the program-address bus activity while the CPU is executing the user program. If an address match is
detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
21.1.1.2
– Breakpoint 1 Register (BP1)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
BP1.15
BP1.14
BP1.13
BP1.12
BP1.11
BP1.10
BP1.9
BP1.8
BP1.7
BP1.6
BP1.5
BP1.4
BP1.3
BP1.2
BP1.1
BP1.0
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s = special
The Breakpoint 1 register is accessible only via background mode read/write commands. Breakpoint registers BP0, BP1,
BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the debug
engine monitors the program-address bus activity while the CPU is executing the user program. If an address match is
detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
21.1.1.3
– Breakpoint 2 Register (BP2)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
BP2.15
BP2.14
BP2.13
BP2.12
BP2.11
BP2.10
BP2.9
BP2.8
BP2.7
BP2.6
BP2.5
BP2.4
BP2.3
BP2.2
BP2.1
BP2.0
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s = special
The Breakpoint 2 register is accessible only via background mode read/write commands. Breakpoint registers BP0, BP1,
BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the debug
engine monitors the program-address bus activity while the CPU is executing the user program. If an address match is
detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
21.1.1.4
– Breakpoint 3 Register (BP3)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
BP3.15
BP3.14
BP3.13
BP3.12
BP3.11
BP3.10
BP3.9
BP3.8
BP3.7
BP3.6
BP3.5
BP3.4
BP3.3
BP3.2
BP3.1
BP3.0
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s = special
The Breakpoint 3 register is accessible only via background mode read/write commands. Breakpoint registers BP0, BP1,
BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the debug
engine monitors the program-address bus activity while the CPU is executing the user program. If an address match is
detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
21.1.1.5
– Breakpoint 4 Register (BP4)
The Breakpoint 4 register is accessible only via background mode read/write commands.
When REGE = 0: This register serves as one of the two data memory address breakpoints. When DME is set in
background mode, the debug engine will monitor the data memory address bus activity while the CPU is executing the
user program. If an address match is detected, a break occurs, allowing the debug engine to take over control of the CPU
and enter debug mode.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
BP4.15
BP4.14
BP4.13
BP4.12
BP4.11
BP4.10
BP4.9
BP4.8
BP4.7
BP4.6
BP4.5
BP4.4
BP4.3
BP4.2
BP4.1
BP4.0
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s = special