Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 78)

DS4830 User’s Guide
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Whenever SCL goes low. If the SCL line is low for a period longer than specified in the timeout register, the I2C
controller concludes that there is a bus error and will set the I2CTOI flag.
For all of these cases, when the I
2
C timeout period is reached, the I2CTOI flag will be set. The setting of I2CTOI can
generate an interrupt if enabled. If the master I
2
C controller is in the process of transferring data when the timeout occurs, the
controller will abort the current transfer and clear the I2CBUSY flag. The I2CBUS flag will continue to be set until a STOP
condition is detected or I2CEN is set to 0.
10.1.5
– Generating a START
To initiate a data transfer, the I
2
C master controller must first issue a START command. The master I
2
C controller’s flow
when attempting to issue a START command is shown in Figure 10-3. A START command is generated by setting the
I2CSTART bit to 1. The I
2
C controller will then determine the state of the I
2
C bus. If the bus is busy (I2CBUS = 1), the
controller will not generate a START until the bus is available. The I 2 C bus is considered busy if another master has
generated a START condition and no corresponding STOP has been detected (the I2CBUS bit is set to 1) or SCL is
being held low.
If the bus is not busy, the I
2
C master controller will attempt to generate a START. Because the SDA line is feedback
into the device, when the master generates a START, it can also detect the START condition. When a start condition is
detected, the I
2
C START interrupt flag (I2CSRI) will be set and an interrupt will be generated if e n a b le d . The
I2CBUS bit will be set to indicate that the I
2
C bus is now in use and the I2CSTART bit will be cleared.
When the I2CSTART bit is set to a 1, the I
2
C controller will start its timeout timer if enabled (I2CTO_M ≠ 0). If the
timer expires before the START can be generated, t h e I
2
C timeout interrupt flag (I2CTOI) will be set and an interrupt
generated if enabled. If a timeout occurs, the I2C master controller will reset to an idle state and the I2CSTART bit will
be cleared.
If the I2CSTART bit is set when the I2C Controller is in the middle of a byte transfer (after the 1st bit rising edge), the
controller will wait for the current byte transfer to finish (after the 9th bit) before generating the START condition. In this
case, the timeout timer will not start counting until after the end of the 9th bit low time.