Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 40)

DS4830 User’s Guide
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5.3 – Interrupt System Operation
The interrupt handler hardware responds to any interrupt event when it is enabled. An interrupt event occurs when an
interrupt flag is set. All interrupt requests are sampled at the rising edge of the clock and can be serviced by the processor
one clock cycle later, assuming the request does not hit the interrupt exception window. The one-cycle stall between
detection and acknowledgement/servicing is due to the fact that the current instruction may also be accessing the stack.
For this reason, the CPU must allow the current instruction to complete before pushing the stack and vectoring to IV. If an
interrupt exception window is generated by the currently executing instruction, the following instruction must be executed,
so the interrupt service routine will be delayed an additional cycle.
Interrupt operation in the DS4830 CPU is essentially a state machine generated long CALL instruction. When the interrupt
handler services an interrupt, it temporarily takes control of the CPU to perform the following sequence of actions:
1. The next instruction fetch from program memory is cancelled.
2. The return address is pushed on to the stack.
3. The INS bit is set to 1 to prevent recursive interrupt calls.
4. The instruction pointer is set to the location of the interrupt service routine (contained in the Interrupt Vector
register).
5. The CPU begins executing the interrupt service routine.
Once the interrupt service routine completes, it should use the RETI instruction to return to the main program. Execution
of RETI involves the following sequence of actions:
1. The return address is popped off the stack.
2. The INS bit is cleared to 0 to re-enable interrupt handling.
3. The instruction pointer is set to the return address that was popped off the stack.
4. The CPU continues execution of the main program.
Pending interrupt requests will not interrupt an RETI instruction; a new interrupt will be serviced after first being
acknowledged in the execution cycle which follows the RETI instruction and then after the standard one stall cycle of
interrupt latency. This means there will be at least two cycles between back-to-back interrupts.
5.3.1
– Synchronous vs. Asynchronous Interrupt Sources
Interrupt sources can be classified as either asynchronous or synchronous. All internal interrupts are synchronous
interrupts. An internal interrupt is directly routed to the interrupt handler that can be recognized in one cycle. All external
interrupts are asynchronous interrupts by nature. When the device is not in stop mode, asynchronous interrupt sources
are passed through a 3-clock sampling/glitch filter circuit before being routed to the interrupt handler. The sampling/glitch
filter circuit is running on the system clock. An interrupt request with a pulse width less than three system clock cycles is
not recognized. Note that the granularity of interrupt source is at module level. Synchronous interrupts and sampled
asynchronous interrupts assigned to the same module produce a single interrupt to the interrupt handler.
5.3.2
– Interrupt Prioritization by Software
All interrupt sources of the DS4830 naturally have the same priority. However, when CPU operation vectors to the
programmed Interrupt Vector address, the order in which potential interrupt sources are interrogated is left entirely up to
the user, as this often depends upon the system design and application requirements. The Interrupt Mask system register
provides the ability to knowingly block interrupts from modules considered to be of lesser priority and manually re-enable
the interrupt servicing by the CPU (by setting INS = 0). Using this procedure, a given interrupt service routine can continue
executing, only to be interrupted by higher priority interrupts. An example demonstrating this software prioritization is
provided in the Handling Interrupts section of Section 19: Programming.
5.3.3
– Interrupt Exception Window
An interrupt exception window is a non interruptable execution cycle. During this cycle, the interrupt handler does not
respond to any interrupt requests. All interrupts that would normally be serviced during an interrupt exception window are
delayed until the next execution cycle.
Interrupt exception windows are used when two or more instructions must be executed consecutively without any delays
in between. Currently, there is a single condition in the DS4830 that causes an interrupt exception window: activation of
the prefix (PFX) register.