Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 119)

DS4830 User’s Guide
119
14.2.4
– Alternate PWM Output
Table 14-3 shows the mapping of each PWM Output. The PWM outputs PW0 to PW7 are also multiplexed with the DAC
output pins. The DS4830 provides the option to select these alternate locations for PW0 to PW7 outputs if PWM
functionality is required along with DAC outputs. When the ALT_LOC is set to ‘1’ during PWM configuration for a PWM
output, the PWM output will be available on this alternate pin. See Table 14-3 for details.
Table 14-3. Alternate PWM Output
PWM Output Pin
DS4830 Pin Number
When ALT_LOC = 0
GPIO Pin
DS4830 Pin Number
When ALT_LOC = 1
GPIO Pin
PW0 32 P0.4 4 P2.0
PW1 33 P0.5 6 P2.1
PW2 34 P6.5 12 P2.2
PW3 35 P1.5 13 P2.3
PW4 36 P1.6 24 P1.0
PW5 37 P1.7 25 P1.3
PW6 38 P6.6 26 P1.1
PW7 40 P2.7 27 P1.2
PW8 30 P0.6 30 P0.6
PW9 29 P0.7 29 P0.7
14.2.5
– PWM DELAY Register (PWMDLYn)
The Delay Register is used to provide a delay when starting the PWM output. By controlling the starting time for each
individual PWM channel, multi phase operation can be achieved.
The number of bits used to program the Delay depends on the resolution programmed in the PWMCFG SFR. For 12 bits
of resolution, the Delay is the lower 12 bits of the PWMDATA register. However if only 7 bits of resolution is selected, only
the lower 7 bits are used to control the Delay of the corresponding PWM Channel. For e.g. if 8-bit resolution is selected,
the maximum delay programmed is limited to 255 (only lower 8 bits are considered).
The Delay resolution also depends on whether Pulse spreading is selected for the corresponding channel. The maximum
delay is scaled correspondingly by 4 or 32 depending on whether 4-slot or 32-slot pulse spreading option is used. For the
above example with 8 bits of resolution, the maximum delay programmed is limited to 256/4 = 64.
Programmed Delay. Max 8 Bits (256 clock cycles),
for 8 bits of Resolution
Figure 14-6: PWM Delay operation without pulse spreading