Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 48)

DS4830 User’s Guide
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case for sequence conversion, where the starting and ending configuration address is the same. The configuration
registers can be viewed as a circular register array where ADSTART does not have to be less than ADEND. For example,
if ADSTART = 1 and ADEND = 5, then the sequence of conversions would be configurations 1, 2, 3, 4, 5. If ADSTART =
5 and ADEND = 1, then the sequence of conversions would be configurations
5, 6, 7,…… 23 , 0, 1.
The ADC has two conversion sequence modes, single and continuous which are set by the ADCONT bit. When the start
conversion bit (ADCONV) is set to ‘1’, the ADC controller starts the ADC conversion sequence. In single sequence mode
(ADCONT=0), the ADCONV bit will remain set until the ADC has finished the conversion of the last channel in the
sequence. In continuous mode (ADCONT=1), the ADCONV bit remains set until the continuous mode is stopped. Writing
a
‘0’ to the ADCONV bit stops the ADC operation at the completion of the current ADC conversion. Writing a ‘1’ to the
ADCONV bit when ADCONV bit is already set to ‘1’ will be ignored by the ADC controller. The ADC should be used in the
continuous mode if temperature conversion or/and sample and hold are used with the ADC conversion sequence.
7.1.3
– Temperature Conversion
The DS4830 allows monitoring of internal die temperature and two external remote temperature measurements. These
temperature channels can be independently enabled by writing a ‘1’ to the corresponding bit location in the Temperature
Control register (TEMPCN). Each temperature sensor has a separate temperature conversion complete flag located in the
ADST register. Data buffer 22, 21 and 20 are reserved for the results of the internal die temperature sensor, external
remote temperature 0 and external remote temperature 1 respectively. The TEMPCN register has separate bits for
interrupt enable and data alignment bit for each temperature sensors.
A DS4830 temperature conversion provides 0.0625 °C of resolution. If temperature conversions are enabled
simultaneously with voltage conversions, the temperature conversions get time slots in between voltage conversions in a
sequence. See Figure 7-3, ADC Frame Sequence for more details. The result of a temperature conversion will always be
copied to their respective data buffers.
Each temperature conversion time is nominally 4.1msec at the lowest ADC Clock. The time required for the ADC to make
a temperature measurement is greater than the time required for a voltage measurement. When a temperature
conversion is performed, t
he ADC’s internal current source forces current into the diode connected to the channel. As the
current is being sourced, the ADC integrates the voltage across the diode. This is known as the integration time (t_int).
The integration time lasts approximately 2 ms. This integration time is a constant and does not scale when the ADC clock
speed is changed. When the integration time is complete, the ADC performs a voltage conversion of the integrated
voltage. The voltage conversion is a normal voltage conversion and will take 30 ADC clock cycles. A temperature
conversion requires that this integration and conversion process be performed twice. The extended acquisition time
function does not apply when in temperature sensing mode. The time required for a complete temperature conversion
can be calculated to be:
2 X (t_int + 30 ADC clocks)
The temperature integration time will be performed concurrently in the background if the ADC is running a sequence of
voltage conversions. The voltage sequence will only be interrupted when the integration time is complete and a
conversion of the integration needs to occur. By performing the integration in the background, the interruption to a voltage
sequence is minimized.
7.1.4
– Sample and Hold Conversion
The DS4830 has two Sample and Hold (S/H) inputs at pins GP2-GP3 and GP12-GP13. These can be independently
enabled or disabled by writing to their corresponding bit locations in the Sample and Hold Control register (SHCN). See
the Sample and Hold description in Section 8. The Sample and Hold uses data buffer 23 and 24 for S/H0 and S/H1
respectively. The Sample and Hold conversion complete flags are located in the ADST register. When enabled with
voltage conversions, the sample and hold conversions get time slots in between voltage conversions. See Figure 7-3,
ADC Frame Sequence for more details. The result of a sample and hold conversion will always be copied to their
respective data buffers.
7.1.5
– ADC Frame Sequence
When all modes (voltage, temperature, and sample and hold) are used simultaneously, the ADC controller uses time
slicing. The ADC controller uses the ADC sequence of voltage conversions as “primary channels” and other channels
(temperature sensors and sample and hold) as secondary channels. The time slicing rules are
1. The primary channels (ADC voltage channels) have priority over the secondary channels (Temperature sensors
or S/Hs).
2. Among secondary channels, temperature conversion has priority over the Sample and Hold.