Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 82)

DS4830 User’s Guide
82
1. If I2CBUF_M is empty, the I
2
C master controller will copy the data from the shift register into I2CBUF_M. The
I2CRXI flag will be set to indicate a received byte is ready to be read. The setting of I2CRXI can generate an
interrupt if enabled.
2. If I2CBUF_M is full, the data in the shift register cannot be copied into I2CBUF_M. This causes a receive overrun
condition. The receive overrun flag, I2CROI, will be set which can generate an interrupt if enabled. I2CBUF_M
will be full if it was not read by software following the reception of a previous byte.
After receiving a byte of data and the I2CRXI flag being set, it is up to software to read I2CBUF_M prior to a second byte
being received. Reading the I2CBUF_M register returns the received data and also clears I2CBUF_M. As long as the
previous byte of data is read from I2CBUF_M before the next byte has completed, receive overrun will not occur.
When receive overrun is detected and I2CROI bit is set, the DS4830 master I
2
C controller will stop outputting SCL clocks
and not clock the acknowledge bit until the receive overrun condition is cleared. The receive overrun condition and the
I2CROI flag can only be cleared by software reading the first byte received from I2CBUF_M. When the receive overrun
condition is cleared, the I
2
C master controller will copy the second byte that was received into I2CBUF_M, and again set
I2CRXI to indicate a byte of data was received. The I
2
C master controller will resume clocking SCL after satisfying SCL
low time requirements.
The master I
2
C controller will continue to automatically clock bytes of data until any of the following conditions occur.
1) A receive overrun condition occurs.
2) A STOP command is issued (I2CSTOP=1) prior to the master I
2
C controller beginning to clock a new byte.
3) The master I
2
C controller has clock stretching enabled and the clock is currently being held low by the master.