Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 116)

DS4830 User’s Guide
116
PWM Output
High Time
128 Cycles
PWM Output
Low Time
384 Cycles
PWM Frame = 512 Cycles
9-bit PWM Operation in Normal Mode
DCYCn = 128
Figure 14-4: PWM Duty Cycle set to 128 with 9-bits resolution
14.2.2
– PWM Configuration Register (PWMCFGn)
This register allows independent configuration of a PWM Channel. Each PWM Channel can be independently disabled or
enabled. Each output can have from 7 to 12 bits of resolution and can be inverted.
The PWM channels 0
– 7 are multiplexed with the DAC outputs. This register allows configuring the output to be present
on this alternate location instead of the original location.
The PWMs can be clocked using the core clock, the peripheral clock or an external clock.
14.2.3
– Pulse Spreading
The DS4830 PWMs have the ability to perform pulse spreading on the output stream. Pulse spreading divides the PWM
frame into equal slots. The DS4830 PWM controller has two pulse spreading options, 4-slot pulse spreading and 32-slot
pulse spreading. These are controlled by 2 bits in the PWMCFGn register (PS4 and PS32). The 4-slot pulse spreading
option is available for all PWM resolutions. The 32-slot pulse spreading option is available for 12-bits PWM operation only.
Pulse spreading allows lower values of external components for the same resolution because the PWM output frequency
is greater.
Slots of Number Frequency Frame PWM Frequency Slot PWM
 
14.2.3.1 4-Slot Pulse Spreading Operation
This mode is selected when PS4 is set to ‘1’ and PS32 is set to ‘0’. During this mode, the PWM controller distributes the
duty cycle over four equal slots. By doing this, the PWM slot frequency becomes 4 times the PWM frame frequency.
For example, 9-bit PWM output with the DCYCn value of 127 with 4-slot pulse spreading enabled produces a PWM output
as shown in the Figure 14-5. The duty cycle of 127 in 512 cycles (9-bit resolution) has been divided over 4 equal slots of
approximately 32 PWM clock cycles.
The algorithm is as follows.
1. Each slot equally gets DCYCn/4 of the PWM cycle counts.
2. If there is 1 residue count, then the first slot gets an extra PWM cycle count.
3. If there are 2 residue counts, then the first two slots get an extra PWM cycle count.
4. If there are 3 residue counts, then the first three slots get an extra PWM cycle count.
Using the above algorithm, (31+1) PWM cycle counts are given to the first three slots and the 31 PWM cycle counts are
assigned to the fourth slot.