Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 102)

DS4830 User’s Guide
102
12.2.3 – Write Collision While Busy
A write collision occurs if an attempt to write the SPIB data buffer is made during a transfer cycle (STBY=1). Since the
shift register is single buffered in the transmit direction, writes to SPIB are made directly into the shift register. Allowing the
write to SPIB while another transfer is in progress could easily corrupt the transmit/receive data. When such a write
attempt is made, the current transfer continues undisturbed, the attempted write data is not transferred to the shift
register, and the control unit sets the Write Collision flag (SPICN.4: WCOL). Setting the WCOL bit to 1 causes an interrupt
if SPI interrupt sources are enabled. Once set, the WCOL bit is cleared only by software or a reset. Normally, write
collisions are associated solely with slave devices since they do not control initiation of transfers and do not have access
to as much information about the SPICK clock as the master. As a master, write collisions are completely avoidable,
however, the control unit detects write collisions for both master and slave modes.
12.3 – SPI Interrupts
Four flags in the SPICN SFR can generate an SPI interrupt when enabled.

Mode Fault (MODF) – This is applicable in Master mode only.

Write Collision (WCOL)

Receive overrun

SPI Transfer Complete
These four bits serve as interrupts flags that allow the system programmer to specify the source of interrupts which may
cause an interrupt request to the CPU. These bits default to 0 on reset and must be cleared by software when set. Once
the SPI Interrupt is enabled by setting the ESPII bit to ‘1’, any of the four SPI interrupt sources can cause an interrupt.