Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 94)

DS4830 User’s Guide
94
1. The I
2
C slave controller is in the idle state and there is no communications on the I
2
C bus. The timer should not
generate interrupts if the I
2
C slave controller is in the idle state regardless of how long SCL is low.
2. The SMBUS mode bit is not set. This ensures the SMBUS timeout functionality does not interfere with normal I
2
C
functionality.
3. SCL is high. The timer is inactive whenever SCL is high. The timer resets when it is inactive.
4. The I
2 C slave controller is disabled or used as a master I 2 C controller. The timer is not needed in this case.
The following description explains when the SMBus timer starts, assuming that all other start conditions are met. When
the DS4830
’s I 2
C slave controller is idle and it receives a START, it will exit the idle state and the timer will become active
(starts counting) any time SCL goes low. If following the start, the master addresses a different slave on the bus, the I
2
C
slave controller will return to the idle state and the timer will reset and become inactive. In short, as soon as SCL goes low
following a START, the SMBus timer will become active until the I
2
C slave controller re-enters idle state.
When a timeout occurs, the timeout bit (I2CTOI) will be set, which can generate an interrupt if enabled. If a timeout
occurs, it may be necessary to reset the I
2
C slave controller. See Resetting the I
2
C Slave Controller for more details.
SMBus mode selection is controlled by the SMB_MOD bit in I2CCN_S register. When the Slave SMBus Mode Operation
bit (SMB_MOD) is set to 1, the SMBUS timeout functionality will be enabled.
11.1.10
– Resetting the I2C Slave Controller
The I
2 C Slave Controller can be reset by disabling the I2C Slave controller by writing ‘0’ at I2CEN = 0 in I2CCN register.
A reset will force the I
2
C slave controller to release both SDA and SCL if they are being held low by the I
2
C slave
controller. The reset may reset few or all bits of I2CCN, I2CST and I2CBUF registers and reset the internal state machine
of the I
2
C slave controller. Following a reset, the I
2
C slave controller must be re-initialized.
11.1.11
– Operation as a Master
The DS4830 contains two I
2
C interfaces, the slave (SDA and SCL) and master (MSDA and MSCL). These are two totally
separate blocks within the DS4830. However, both of the blocks are identical. Because of this, it is possible to operate
the slave as a master and also operate the master as a slave.
To operate the slave (SDA and SCL) as a master I
2
C interface, the I2CMST bit in I2CCN_S needs to be set to a 1. When
the slave is operating as a master, it will use the same registers (I2CCN_S, I2CST_S, etc) that it uses for slave operation.
However the bits in these registers will have different functionality, as described in the I
2 C Master Interface Section. The
I2CCN_S.SMB_MOD bit has no effect when the interface is operating in master mode. See the I
2
C Master Interface
section for details on initializing and using a master I
2
C interface.
Note: When the I
2
C slave interface is changed to operate in master mode, the I
2
C bootloader will not be available.
Note: When the I
2
C slave interface is disabled, the I
2
C bootloader will not be available.