Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 166)

DS4830 User’s Guide
166
21.3.3
– In-Circuit Debug Control Register (ICDC, M2[1Ah])
Bit 7 6 5 4 3 2 1 0
Name DME - REGE - CMD3 CMD2 CMD1 CMD0
Reset 0 0 0 0 0 0 0 0
Access rs r Rs r rs rs rs rs
r = read, s = special
BIT
NAME DESCRIPTION
7 DME Debug Mode Enable (DME). When this bit is cleared to 0, background mode commands may
be executed, but breakpoints are disabled. When this bit is set to 1, breakpoints are enabled
while background mode commands still may be entered. This bit may only be set or cleared
from background debug mode. This bit has no meaning for the ROM code.
6 Reserved Reserved. Do not write to this bit.
5 REGE Break-On Register Enable. The REGE bit is used to enable the break-on register function.
When REGE bit is set to 1, BP4 and BP5 are used as register breakpoints. A break occurs
when the content of BP4 is matched with the destination address of the current instruction. For
BP5, a break occurs only on a selected data pattern for a selected destination register
addressed by BP5. The data pattern is determined by the contents in the ICDA and ICDD
register. The REGE bit alone does not enable register breakpoints, but simply changes the
manner in which BP4, BP5 are used. The DME bit still must be set to a logic 1 for any
breakpoint to occur. This bit has no meaning for the ROM code.
4 Reserved Reserved. Do not write to this bit.
3:0 CMD3:0 These bits reflect the current host command in debug mode. These bits are set by the debug
engine and allow the ROM code to determine the course of action
CMD3:0 Action
0000 No operation
0001 Read register
0010 Read data memory
0011 Read stack memory
0100 Write register
0101 Write data memory
1000 Unlock password
1001 Read selected register
Other Reserved