Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 130)

DS4830 User’s Guide
130
15.2.5 – GPIO Port 0 External Interrupt Flag Register (EIF0)
Bit # 7 6 5 4 3 2 1 0
Name IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
These bits are set when a negative edge (IESP0.n = 1) or a positive edge (IESP0.n = 0) is detected on the P0.n pin.
Setting any of the bits to 1 will generate an interrupt to the CPU if the corresponding interrupt is enabled. These bits will
remain set until cleared by software or a reset. These bits must be cleared by software before exiting the interrupt service
routine or another interrupt will be generated as long as the bit remains set.
15.2.6
– GPIO Port 0 External Interrupt Enable Register (EIE0)
Bit # 7 6 5 4 3 2 1 0
Name EX7 EX6 EX5 EX4 EX3 EX2 EX1 EX0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Setting any of these bits to 1 will enable the corresponding external interrupt. Clearing any of the bits to 0 will disable the
corresponding interrupt function.
15.3
– GPIO Port 1 Register Descriptions
Port 1 provides 8 GPIO pins that are multiplexed with various serial and analog interfaces. These include 3-Wire, I2C
Master, SPI Master, DAC, and PWM functionality. Each serial interface has control through enable bit defined in its
control register. 3-Wire has enable bit TWEN in TWR register. I2C Master has master enable bit I2CEN in I2CCN_M
register. Similarly, SPI Master has SPI Master enable bit SPIEN in SPICN_M. DAC function is enabled when DACCFG.n
is set to either “10b” or “01b” (where n = 3, 4 or 5). REFINB (Pin1.4) is configured as external reference when DACCFG.n
is set to “01b” for any DACn (where n = 4 to 7). PWM is enabled when corresponding PWM local enable and PWM master
enable is set to ‘1’.
Port 1 also provides GPIO interrupts on all of the pins. A GPIO interrupt can be generated when the pin is being operated
as a GPIO, or a special. Three additional registers, EIF1, EIE1, and EIES1 are used to control the GPIO interrupts
15.3.1
– GPIO Direction Register Port 1 (PD1)
Bit # 7 6 5 4 3 2 1 0
Name PD1_7 PD1_6 PD1_5 PD1_4 PD1_3 PD1_2 PD1_1 PD1_0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
PD1 is an 8-bit register used to determine the direction of the pins when they are used as GPIO pins. Each pin is
independently controlled by its direction bit. When PD1.n (n = 0 to 7) is set to 1, the pin is an output; data in the PO1.n bit
will be driven on the pin. When PD1.n is cleared to 0, the pin is an input, and allows an external signal to drive the pin.
Note that each port pin has a weak pull-up circuit when functioning as an input. The P channel pull-up transistor is
controlled by the PO1.n bit. If PO1.n is set to 1, the corresponding weak pull-up is turned on, if the PO1.n bit is cleared to
0, the weak pull-
up is turned off and the pin’s input is high-impedance. When the Port 1 pins are operating as PWM pins,
the data in PD1 will not affect PWM operation.
15.3.2
– GPIO Output Register Port 1 (PO1)
Bit # 7 6 5 4 3 2 1 0
Name PO1_7 PO1_6 PO1_5 PO1_4 PO1_3 PO1_2 PO1_1 PO1_0
Reset 1 1 1 1 1 1 1 1
Access rw rw rw rw rw rw rw rw
PO1 is an 8-bit register that controls the output data of a GPIO pin. If the pin is setup to be an output (PD1.n = 1), the
data in PO1.n will be output on the pin. If the pin is set as an input (PD1.n = 0), setting PO1.n to a 1 enables a p-channel
weak pull-
up, otherwise the pin’s input is high impedance.
When the Port 1 pins are operating as PWM pins, the data in PO1 will not affect PWM operation. Changing the direction
of the pin does not change the data content of PO1.n.