Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 64)

DS4830 User’s Guide
64
8.1.5 – Sample and Hold Data Reading
Each sample and hold has defined data buffer locations where the ADC controller writes sample and hold results after the
ADC conversion. The data buffer location 23 and 24 are reserved for Sample and Hold 0 and 1 respectively. The ADC
controller uses ADCG1 (1.2V full scale) for ADC conversion of the sampled signal of both sample and holds.
8.1.6
– Sample and Hold Interrupts
The DS4830 sample and hold has two interrupt flags SH0DAI and SH1DAI in the ADST register. The SH1DAI bit is used
only when both Sample and Hold are enabled in the dual mode operation. In single mode operation, SH0ADI is set only
when:
1. Both sample and holds are enabled, then after the ADC conversion of both samples.
2. If only one sample and hold is enabled, then after the ADC conversion of the enabled sample and hold.