Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 129)

DS4830 User’s Guide
129
15.2 – GPIO Port 0 Register Descriptions
Port 0 provides eight GPIO pins that are multiplexed with ADC, DAC, Sample and Hold1 and PWM functionality. ADC
function is enabled when PINSEL.n is set to ‘1’ (where n = 12 to 15). Single or Differential ADC mode is selected by
ADDATA.DIFF bit during ADC configuration (when ADCN.CFG is set to ‘1’). DAC function is enabled when DACCFG.n is
set to either “10b” or “01b” (where n = 0 or 1). Sample and Hold-1 is enabled when SHCN.SMP_HLD1 is set to ‘1’. PWM
is enabled when corresponding PWM local enable and PWM master enable is set to ‘1’.
Port 0 also provides GPIO interrupts on all of the pins. A GPIO interrupt can be generated when the pin is being operated
as a GPIO, or a special. Three additional registers, EIF0, EIE0, and EIES0 are used to control the GPIO interrupts
15.2.1
– GPIO Direction Register Port 0 (PD0)
Bit # 7 6 5 4 3 2 1 0
Name PD0_7 PD0_6 PD0_5 PD0_4 PD0_3 PD0_2 PD0_1 PD0_0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
PD0 is an 8-bit register used to determine the direction of the pins when they are used as GPIO pins. Each pin is
independently controlled by its direction bit. When PD0.n (n = 0 to 7) is set to
‘1’, the pin is an output; data in the PO0.n bit
will be driven on the pin. When PD0.n is cleared to ‘0’, the pin is an input and allows an external signal to drive the pin.
Note that each port pin has a weak pull-up circuit when functioning as an input. The P channel pull-up transistor is
controlled by the PO0.n bit. If PO0.n is set to
‘1’, the corresponding weak pull-up is turned on, if the PO0.n bit is cleared to
‘0’, the weak pull-up is turned off and the pin’s input is high-impedance.
15.2.2
– GPIO Output Register Port 0 (PO0)
Bit # 7 6 5 4 3 2 1 0
Name PO0_7 PO0_6 PO0_5 PO0_4 PO0_3 PO0_2 PO0_1 PO0_0
Reset 1 1 1 1 1 1 1 1
Access rw rw rw rw rw rw rw rw
PO0 is an 8-bit register that controls the output data of a GPIO pin. If the pin is setup to be an output (PD0.n = 1), the
data in PO0.n will be output on the pin. If the pin is set as an input (PD0.n = 0), setting PO0.n to a
‘1’ enables a p-channel
weak pull- up, otherwise the pin’s input is high impedance.
When the Port 0 pins are operating as PWM pins, the data in PO0 will not affect PWM operation. Changing the direction
of the pin does not change the data content of PO0.n.
15.2.3
– GPIO Input Register for Port 0 (PI0)
Bit # 7 6 5 4 3 2 1 0
Name PI0_7 PI0_6 PI0_5 PI0_4 PI0_3 PI0_2 PI0_1 PI0_0
Reset s s s s s s s s
Access r r r r r r r r
PI0 is an 8-bit register which contains the data that is applied to the GPIO pins. The PI0 input register contains valid input
data even when the pin is not operating as a GPIO. The reset value for this register is dependent on the logical states
applied to the pins. Note that each pin has a weak pull-up circuit when functioning as an input and the P channel pull-up
transistor is controlled by the PO0.n bit.
15.2.4
– GPIO Port 0 External Interrupt Edge Select Register (EIES0)
Bit # 7 6 5 4 3 2 1 0
Name IT7 IT6 IT5 IT4 IT3 IT2 IT1 IT0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
The EIES0 register sets the interrupt edge select to trigger an interrupt on either a rising or falling edge. Setting the
IESP0_n bits to 0 will trigger the corresponding interrupt on a positive edge. When these bits are set to a 1, the interrupt
will be on a negative edge.