Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 28)

DS4830 User’s Guide
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3.10 Prefix Register (PFX[n], Bh[n])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
BIT NAME DESCRIPTION
15:0 PFX[n][15:0]
The Prefix register provides a means of supplying an additional 8 bits of high-order data for use by the succeeding instruction
as well as providing additional indexing capabilities. This register will only hold any data written to it for one execution cycle,
after which it will revert to 0000h. Although this is a 16-bit register, only the lower 8 bits are actually used for prefixing purposes
by the next instruction. Writing to or reading from any index in the Prefix module will select the same 16-bit register. However,
when the Prefix register is written, the index n used for the PFX[n] write also determines the high-order bits for the register
source and destination specified in the following instruction.
The index selection reverts to 0 (default mode allowing selection of registers 0h to 7h for destinations) after one cycle in the
same manner as the contents of the Prefix register.
WRITE TO SOURCE REGISTER
RANGE
DESTINATION REGISTER
RANGE
PFX[0] 0h to Fh 0h to 7h
PFX[1] 10h to 1Fh 0h to 7h
PFX[2] 0h to Fh 8h to Fh
PFX[3] 10h to 1Fh 8h to Fh
PFX[4] 0h to Fh 10h to 17h
PFX[5] 10h to 1Fh 10h to 17h
PFX[6] 0h to Fh 18h to 1Fh
PFX[7] 10h to 1Fh 18h to 1Fh
3.11 Instruction Pointer Register (IP, Ch[0h])
Initialization: This register is cleared to 8000h on all forms of reset.
Access: Unrestricted direct read/write access.
BIT DESCRIPTION
15:0
This register contains the address of the next instruction to be executed and is automatically incremented by 1 after each
program fetch. Writing an address value to this register will cause program flow to jump to that address. Reading from this
register will not affect program flow.
3.12 Stack Pointer Register (SP, Dh[1h])
Initialization: This register is cleared to 000Fh on all forms of reset.
Access: Unrestricted direct read/write access.
BIT DESCRIPTION
15:4 Reserved; all reads return 0.
3:0
These four bits indicate the current top of the hardware stack, from 0h to Fh. This pointer is incremented after a value is
pushed on the stack and decremented before a value is popped from the stack.
3.13 Interrupt Vector Register (IV, Dh[2h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
BIT DESCRIPTION
15:0
This register contains the address of the interrupt service routine. The interrupt handler will generate a CALL to this address
whenever an interrupt is acknowledged.
3.14 Loop Counter 0 Register (LC[0], Dh[6h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
BIT DESCRIPTION
15:0
This register is used as the loop counter for the DJNZ LC[0], src operation. This operation decrements LC[0] by one and
then jumps to the address specified in the instruction by src if LC[0] = 0.
3.15 Loop Counter 1 Register (LC[1], Dh[7h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
BIT DESCRIPTION
15:0
This register is used as the loop counter for the DJNZ LC[1], src operation. This operation decrements LC[1] by one and
then jumps to the address specified in the instruction by src if LC[1] = 0.