Ds4830 user’s guide – Maxim Integrated DS4830 Optical Microcontroller User Manual
Page 109
DS4830 User’s Guide
109
12.5.4.2
– SPI Configuration Register (SPICF_S)
SPICF_S Register Address: M1 [13h]
Bit
7
6
5
4
3
2
1
0
Name
ESPII
SAS
-
-
-
CHR
CKPHA
CKPOL
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
r
r
r
rw
rw
rw
BIT
NAME
DESCRIPTION
7
ESPII
SPI Interrupt Enable.
Setting this bit to ‘1’ enables the SPI interrupt when MODF, WCOL,
ROVR or SPIC flags are set. Clearing this bit to ‘0’ disables the SPI interrupt.
6
SAS
Slave Active Select.
In Slave Mode, this bit is used to determine the SSPICS active state. When the SAS is
cleared to ‘0’, the SSPICS is active low and will respond to an external low signal. When
the SAS is set to ‘1’, the SSPICS is active high.
5:3
Reserved
Reserved, Read Returns 0.
2
CHR
Character Length Bit. The CHR bit determines the character length for an SPI transfer
cycle. A character can consist of 8 or 16 bits in length. When CHR bit is ‘0’, the character is
8 bits; when CHR is set to ‘1’, the character is 16 bits.
1
CKPHA
SPI Clock Phase Select. This bit is used with the CKPOL bit to determine the SPI transfer
format. When the CKPHA is set to
‘1’, the SPI will sample input data at an inactive edge.
When the CKPOL is cleared to 0, the SPI will sample input at an active edge.
0
CKPOL
SPI Clock Polarity Select. This bit is used with the CKPHA bit to determine the SPI
transfer format. When the CKPOL is set to
‘1’, the SPI uses the clock falling edge as
an active edge. When the CKPOL is cleared to 0, the SPI selects the clock rising edge as
an active edge.
12.5.4.3
– SPI Clock Register (SPICK_S)
SPICK_S Register Address: M1 [14h]
Bit
7
6
5
4
3
2
1
0
Name
SPICK_S[7:0]
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
7:0
SPICK_S[7:0]
The register has no function when operation in slave mode and clock generation circuitry is
disabled.
12.5.4.4
– SPI Data Buffer Register (SPIB_S)
SPIB_S Register Address: M1 [04h]
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
SPIB_S[15:0]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access*
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
*Unrestricted read, write is allowed outside of a transfer cycle; when the STBY bit is set, write is blocked and will cause
write collision error.
BIT
NAME
DESCRIPTION
15:0
SPIB_S[15:0]
SPI Data Buffer Bits. Data for SPI is read from or written to this location. The serial
transmit and receive buffers are separate but both are addressed at this location.