Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 112)

DS4830 User’s Guide
112
13.2 – 3-Wire Register Descriptions
The 3-Wire interface is controlled by two SFR registers. These are the 3-Wire Control Register TWR and Data and
Address Register DADDR. The TWR register configures and controls 3-Wire interface. The DADDR is used in 3-Wire
read and write operation. These registers are located at Module 2.
13.2.1
– 3-Wire Control Register (TWR)
Register Address: M2 [0Ah]
Bit
7 6 5 4 3 2 1 0
Name TWEN TWCP[2:0] TWIE TWCSDIS TWI BUSY
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw r
BIT NAME DESCRIPTION
7 TWEN 3-Wire Enable. This bit enables the 3- Wire interface. When this bit is set to ‘1’, the 3-
Wire interface is enabled. When this bit is cleared, the 3-Wire function is disabled.
6:4 TWCP[2:0] 3-Wire Clock Period. These bits are used for setting the 3-Wire MCL clock period.
TWCP[2:0] MCL Clock Frequency (Period)
000 1 MHz (1000nSec)
001 714 KHz (1400nSec)
010 555 KHz (1800nSec)
011 454 KHz (2200nSec)
100 384 KHz (2600nSec)
101 333 KHz (3000nSec)
110 294 KHz (3400nSec)
111 263 KHz (3800nSec)
3 TWIE 3-Wire Interrupt Enable. Setting this bit to ‘1’ will enable an interrupt when the 3-Wire
data transfer is completed. Clearing this bit will disable the 3-Wire data transfer complete
interrupt.
2 TWCDIS 3-Wire Chip Select disable. Setting this bit to ‘1’, will disable the chip select and the 3-
Wire Master interface will not control the chip select MCS during the communication. In
chip select disable mode, application program should control the 3-Wire chip select by
any GPIO. Clearing this bit will enable MCS as active chip select and it is set to HIGH
(See Figure 13-1) at start of 3-Wire data communication and set to LOW once the 3-Wire
data communication is completed.
1 TWI 3-Wire Interrupt. This bit is set to ‘1’ when data transfer is completed. This bit can
generate interrupt if TWIE bit is enabled. Once set, it should be cleared by software.
0 BUSY 3-Wire Busy. This bit is set to ‘1’ when data is written to the DADDR register and it
indicates that the data transfer is in progress. This bit is reset to ‘0’ once the data
transfer is completed. This is also reset to zero when 3-Wire operation is disabled (the
TWEN bit is ‘0’). This is read only bit.
13.2.2
– Data and Address Register (DADDR)
Register Address: M2 [04h]
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ADDR[15:9] RWN DATA[7:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
BIT NAME DESCRIPTION
15:9 ADDR[6:0] 3-Wire Address. These bits specify Slave device internal register address.
8 RWN Read or Write Select. When this bit is set to ‘1’, the 3-Wire ‘Read’ operation is
performed. When this bit is ‘0’, the 3-Wire ‘Write’ operation is performed.
7:0 DATA[7:0] 3-Wire Data. During 3- Wire ‘Read’ operation (RWN = 1), the master writes the read data
from the 3-Wire bus at these bits. During 3- Wire ‘Write’ operation (RWN = 0), the master
sends data written at these bits on the 3-Wire bus.
Important Note: The entire DADDR register should be written at once instead of writing individual bits or fields.