Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 105)

DS4830 User’s Guide
105
12.4.3 – SPI Master Register Descriptions
SPI Master Module has four SFR registers. These are SPICN_M, SPICF_M, SPICK_M and SPIB_M. The SPI control
register SPICN_M and SPI configuration register SPICF_M controls and configures the Serial Peripheral Interface
respectively. The SPI Clock Register SPICK_M configures SPI Baud rate in Master mode. The SPI Buffer SPIB_M is used
in SPI data transfer. SPI Master SFRs are located in Module 5.
12.4.3.1
– SPI Control Register (SPICN_M)
SPICN_M Register Address: M5 [12h]
Bit 7 6 5 4 3 2 1 0
Name STBY SPIC ROVR WCOL MODF MODFE MSTM SPIEN
Reset 0 0 0 0 0 0 0 0
Access r rw rw rw rw rw rw rw
BIT NAME DESCRIPTION
7 STBY Write Transfer Busy Flag. This bit indicates the current status of the SPI module. STBY is
set to ‘1’ when SPI transfer cycle is started and is cleared to ‘0’ when the transfer cycle is
completed. This bit is controlled by hardware and is read only for user software.
6 SPIC SPI Transfer Complete Flag. This bit indicates the completion of a transfer cycle when set
to ‘1’. This bit must be cleared to ‘0’ by software once set. Setting this bit to logic ‘1’ by
software will cause an interrupt if enabled.
5 ROVR Receive Overrun Flag. This bit indicates a receive overrun when set to ‘1’. This is caused
if two or more characters are received since the last read by the processor. The newer
data is lost.
This bit must be cleared to ‘0’ by software once set. Setting this bit to logic ‘1’
by software will cause an interrupt if enabled.
4 WCOL Write Collision Flag. This bit indicates a write collision when set to ‘1’. This is caused by
attempting to write to the SPIB while a transfer cycle is in progress. . This bit must be
cleared to ‘0’ by software once set. Setting this bit to logic ‘1’ by software will cause an
interrupt if enabled.
3 MODF Mode Fault. This bit is the mode fault flag when the SPI is operating as a master If the
MODFE bit is set, the active signal that causes a mode fault error is defined in the SAS bit.
If the SAS bit is cleared to 0, a low MSPICS signal will trigger a mode fault error. If the SAS
bit is set to 1, a high MSPICS signal will indicate that the mode fault error has occurred.
This bit must be cleared to ‘0’ by software once set. Setting this bit to logic ‘1’ by software
will cause an interrupt if enabled. This flag has no meaning in slave mode.
2 MODFE Mode Fault Enable. When set to ‘1’, MSPICS will be utilized for mode fault detection
during SPI master mode operation. When cleared to ‘0’, the MSPICS input has no function
and its pin can be used for other purposes.
1 MSTM Master Mode Enable. When set to ‘1’, the SPI module will operate in Master mode when
the SPI module is enabled (SPIEN = 1). When set to ‘0’, SPI module will operate in Slave
mode when the SPI module enabled (SPIEN = 1).
0 SPIEN SPI Enable. Setting this bit to ‘1’, enables the SPI Module. Setting this bit to ‘0’, disables
the SPI module.