Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 131)

DS4830 User’s Guide
131
15.3.3
– GPIO Input Register for Port 1 (PI1)
Bit # 7 6 5 4 3 2 1 0
Name PI1_7 PI1_6 PI1_5 PI1_4 PI1_3 PI1_2 PI1_1 PI1_0
Reset s s s s s s s s
Access r r r r r r r r
PI1 is an 8-bit register which contains the data that is applied to the GPIO pins. The PI1 input register contains valid input
data even when the pin is not operating as a GPIO. The reset value for this register is dependent on the logical states
applied to the pins. Note that each pin has a weak pull-up circuit when functioning as an input and the P channel pull-up
transistor is controlled by the PO1.n bit.
15.3.4
– GPIO Port 1 External Interrupt Edge Select Register (EIES1)
Bit # 7 6 5 4 3 2 1 0
Name IT7 IT6 IT5 IT4 IT3 IT2 IT1 IT0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
The EIES1 register sets the interrupt edge select to trigger an interrupt on either a rising or falling edge. Setting the
IESP1_n bits to 0 will trigger the corresponding interrupt on a positive edge. When these bits are set to a 1, the interrupt
will be on a negative edge.
15.3.5
– GPIO Port 1 External Interrupt Flag Register (EIF1)
Bit # 7 6 5 4 3 2 1 0
Name IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
These bits are set when a negative edge (IESP1.n = 1) or a positive edge (IESP1.n = 0) is detected on the P1.n pin.
Setting any of the bits to 1 will generate an interrupt to the CPU if the corresponding interrupt is enabled. These bits will
remain set until cleared by software or a reset. These bits must be cleared by software before exiting the interrupt service
routine or another interrupt will be generated as long as the bit remains set.
15.3.6
– GPIO Port 1 External Interrupt Enable Register (EIE1)
Bit # 7 6 5 4 3 2 1 0
Name EX7 EX6 EX5 EX4 EX3 EX2 EX1 EX0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Setting any of these bits to 1 will enable the corresponding external interrupt. Clearing any of the bits to 0 will disable the
corresponding interrupt function.
15.4
– GPIO Port 2 Register Descriptions
Port 2 provides eight GPIO pins that are multiplexed with the ADC, PWM, DAC and External reference (REFINA). ADC
function is enabled when PINSEL.n is set to ‘1’ (where n = 0, 1, 6 to 9). Single or Differential ADC mode is selected by
ADDATA.DIFF bit during ADC configuration (when ADCN.CFG is set to ‘1’). DAC function is enabled when DACCFG.n is
set to either “10b” or “01b” (where n = 7). PWM is enabled when corresponding PWM local enable and PWM master
enable is set to ‘1’. REFINA (Pin2.6) is configured as external reference when DACCFG.n is set to “01b” for any DACn
(where n = 0 to 3).
Port 2 also provides GPIO interrupts on all of the pins. A GPIO interrupt can be generated when the pin is being operated
as a GPIO, or a special. Three additional registers, EIF2, EIE2, and EIES2 are used to control the GPIO interrupts
15.4.1
– GPIO Direction Register Port 2 (PD2)
Bit # 7 6 5 4 3 2 1 0
Name PD2_7 PD2_6 PD2_5 PD2_4 PD2_3 PD2_2 PD2_1 PD2_0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw