Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 80)

DS4830 User’s Guide
80
10.1.7 – Transmitting a Slave Address
The first byte after an I
2
C start or restart condition is the slave address byte. This byte, which is transmitted by the master,
contains seven bits of slave address followed by the R/W bit. The transmission of the slave address begins with writing
7bit slave address + the R/W bit to I2CBUF_M.
Figure 10-4 shows the format for slave address 36h in write mode. The address bits A[6:0], which is the slave address
the R/W bit is written to I2CBUF_M[6:0]. 0
th
bit of I2CBUF_M is copied to 0
th
bit I2CMODE of I2CSLA_M register. When the
0
th bit is ‘1’, the I2C master is operating in receiver mode (data read from slave). When the 0 th bit is ‘0’, the I2C master is
operating in transmitter mode (data write to slave).
Figure 10-4: Slave Address Format
After the slave address has been written to I2CBUF_M, the I
2
C master controller will set the I2CBUSY bit to indicate the
controller is actively participating in a transaction. The eight bits in I2CBUF_M[7:0] will be transmit on SDA. The data for
the 8
th
bit transmit, which is the R/W bit, is copied in the I2CMODE bit of the I2CSLA_M register. The I
2
C master then
issues the 9
th
clock, which is for the acknowledge bit, and reads SDA for an acknowledgment from a slave device. The
I
2
C master controller then performs the following steps. This is illustrated in Figure 10-5.

Set the I2CNACKI bit with the value of the received acknowledgement.

The I2CTXI bit will then be set to indicate a byte was transmit.

Clear the I2CBUSY flag.
Upon transmitting the slave data byte (7 bits of slave address + R/W bit + acknowledge), the I
2
C master controller will enter
one of the three states.

Data Transmit: The I2CMODE (R/W) bit was set to a 0, indicating that the master will be writing data to a slave
device. The DS4830 will retain control of the SDA line.

Data Receive: The I2CMODE (R/W) bit was set to a 1, indicating that the master will be receiving data from a
slave. The DS4830 releases control of SDA to allow a slave device to output data. The DS4830 Master I
2
C
controller automatically begins clocking bytes of data from the slave.
 The slave address was NACK’d. The master I 2
C controller will retain control of SDA and is able to transmit data.
10.1.8
– Transmitting Data
The DS4830 I
2
C Master Controller enters into data transmission mode after transmitting a slave address with the R/W bit
(I2CMODE) set to a 0. The steps of data transmission are shown in Figure 10-5. Data transmission is started by software
loading a byte of data into the I2CBUF_M register. Loading I2CBUF_M causes the I2CBUSY bit to be set. Once set,
writes to I2CBUF_M will be ignored. The first bit of data (most significant bit) will be shifted to SDA when SCL is low.
Each of the next seven bits will then be shifted following high to low transitions of SCL.
Following the 8
th
bit of data (least significant bit) being shifted to SDA, the SDA line will be released by the DS4830 master
controller. This allows the slave to signal an ACK or NACK during the 9
th
clock cycle. The DS4830 I
2
C master controller
samples the acknowledge bit following the 9
th
SCL rising edge. After the acknowledge bit is sampled, the DS4830 I
2
C
master controller will perform the following tasks:

Set or clear the I2CNACKI flag to reflect the received acknowledge bit. The setting of I2CNACKI can generate an
interrupt if enabled.

Set the I2CTXI flag to indicate that the I
2
C master controller transmit a complete byte. This can generate an
interrupt if enabled.

Clear the I2CBUSY flag to indicate that the I
2
C master controller is not actively participating in the transfer of data.