Maxim Integrated DS4830 Optical Microcontroller - Manual (Page 43)

DS4830 User’s Guide
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The DAC Data register programs the DAC for a particular voltage output depending on the value of this register and the
reference setting. The DAC outputs are voltage buffered and have the capability to sink or source current. Each DAC
output has an output impedance which limits the DAC operating range if configured to sink current (refer to the DS4830 IC
data sheet). The DAC output voltage is maintained during any type of reset except POR. All DACs, REFINA and REFINB
pins default to GPIO on reset.
6.1.1
– Reference Selection
Each DAC can be independently enabled with 2.5V internal reference or external reference. Each DAC has two bits in the
DAC configuration register (DACCFG) which are used to enable or disable the DAC with either an internal or an external
reference.
Any DAC can be enabled for using the internal reference by writing 10b at the corresponding location in the DACCFG
register. The internal reference automatically powers-down when none of the 8 DACs use it as a reference source.
The external reference at REFINA (Port2.6) is selected by writing 01b at the corresponding location in the DACCFG for
DAC0-3. The REFINA automatically becomes GPIO when none of the lower 4 DACs (DAC0 to DAC3) use REFINA as its
reference. The external reference at REFINB (Port1.4) is selected by writing 01b at the corresponding location in the
DACCFG register for DAC4-7. The REFINB pin automatically becomes GPIO when none of the upper 4 DACs (DAC4 to
DAC7) use REFINB as its reference.
6.1.2
– Requirement for Enabled DACs
If a DAC output will be used during the lifetime of the DS4830, the DAC must always be enabled to guarantee meeting the
INL and offset specifications in the DS4830 IC data sheet Electrical Characteristics table. This requirement can be met by
setting the DAC’s configuration bits (DACCFGx) to 01b or 10b at device power on. To disable a DAC that is being used,
the DAC must be set to either the reference voltage (DACDx = 0FFFh) or to 0V (DACDx = 0000h). If a pin will be used for
a DAC, it should be used only for the DAC functi
on. The pin’s function should not be switched between DAC and PWM or
switched between DAC and GPIO.
6.2 – DAC Register Descriptions
The DAC module has total 9 SFR registers. These are DAC Configuration Register DACCFG and 8 DAC Data registers
DACDx (DACD0 to DACD7). The DACCFG configures all DACs and the data register DACDx (DACD0-DACD7) controls
the corresponding DAC output voltage. These SFR’s are located in module 4.