Maxim Integrated MAXQ Family User Manual

Maxq family user’s guide

Table of contents

Document Outline

TABLE OF CONTENTS:
SECTION 1: OVERVIEW
- 1.1 Instruction Set
- 1.2 Harvard Memory Architecture
- 1.3 Register Set
- 1.4 MAXQ10 and MAXQ20 Microc...
SECTION 2: ARCHITECTURE
- 2.1 Instruction Decoding
- 2.2 Register Space
- 2.3 Memory Organization
- 2.4 Pseudo-Von Neumann Memor...
- 2.5 Pseudo-Von Neumann Memor...
- 2.6 Data Alignment
  - 2.6.1 Memory Management Unit
- 2.7 Clock Generation
- 2.8 Interrupts
- 2.9 Operating Modes
SECTION 3: PROGRAMMING
- 3.1 Addressing Modes
- 3.2 Prefixing Operations
- 3.3 Reading and Writing Regi...
- 3.4 Reading and Writing Regi...
- 3.5 Using the Arithmetic and...
- 3.6 Processor Status Flag Op...
- 3.7 Controlling Program Flow
- 3.8 Handling Interrupts
  - 3.8.1 Conditional Return fro...
- 3.9 Accessing the Stack
- 3.10 Accessing Data Memory
- 3.11 Using the Watchdog Timer
SECTION 4: SYSTEM REGISTER DESCRIPTIONS
- 4.1 Accumulator Pointer Regi...
- 4.2 Accumulator Pointer Cont...
- 4.3 Processor Status Flags R...
- 4.4 Interrupt and Control Re...
- 4.5 Interrupt Mask Register ...
- 4.6 System Control Register ...
- 4.7 Interrupt Identification...
- 4.8 System Clock Control Reg...
- 4.9 Watchdog Control Registe...
- 4.10 (MAXQ10) Accumulator n ...
- 4.11 (MAXQ20) Accumulator n ...
- 4.12 Prefix Register (PFX[n]...
- 4.13 Instruction Pointer Reg...
- 4.14 Stack Pointer Register ...
- 4.15 Interrupt Vector Regist...
- 4.16 Loop Counter 0 Register...
- 4.17 Loop Counter 1 Register...
- 4.18 Frame Pointer Offset Re...
- 4.19 Data Pointer Control Re...
- 4.20 General Register (GR, E...
- 4.21 General Register Low By...
- 4.22 Frame Pointer Base Regi...
- 4.23 General Register Byte-S...
- 4.24 General Register High B...
- 4.25 General Register Sign E...
- 4.26 Frame Pointer Register ...
- 4.27 Data Pointer 0 Register...
- 4.28 Data Pointer 1 Register...
SECTION 5: PERIPHERAL REGISTER MODULES
SECTION 6: GENERAL-PURPOSE I/O MODULE
- 6.1 I/O Port: Type A
- 6.2 I/O Port: Type B
- 6.3 I/O Port: Type C
- 6.4 I/O Port: Type D
- 6.5 I/O Port Peripheral Regi...
SECTION 7: TIMER/COUNTER 0 MODULE
- 7.1 Timer 0
- 7.2 Timer/Counter 0 Peripher...
SECTION 8: TIMER/COUNTER 1 MODULE
- 8.1 Timer 1
- 8.2 Timer/Counter 1 Peripher...
- 8.3 Time-Base Selection for ...
SECTION 9: TIMER/COUNTER 2 MODULE
- 9.1 Timer 2
- 9.2 Modes of Operation
- 9.3 Timer 2 Capture Applicat...
- 9.4 Timer/Counter 2 Peripher...
- 9.5 Low-Speed Infrared Trans...
  - 9.5.1 Subcarrier Generation ...
  - 9.5.2 Transmit Baseband Modu...
- 9.6 IR Peripheral Register
  - 9.6.1 Infrared Control Regis...
SECTION 10: SERIAL I/O MODULE
- 10.1 UART Modes
- 10.2 Baud-Rate Generation
- 10.3 Framing Error Detection
- 10.4 UART Peripheral Registers
SECTION 11: SERIAL PERIPHERAL INTERFACE (SPI) MODULE
- 11.1 SPI Transfer Formats
- 11.2 SPI Character Lengths
- 11.3 SPI Transfer Baud Rates
- 11.4 SPI System Errors
- 11.5 SPI Master Operation
- 11.6 SPI Slave Operation
- 11.7 SPI Peripheral Registers
SECTION 12: HARDWARE MULTIPLIER MODULE
- 12.1 Hardware Multiplier Org...
- 12.2 Hardware Multiplier Con...
- 12.3 Register Output Selection
  - 12.3.1 Signed-Unsigned Opera...
  - 12.3.2 Operand Count Selection
- 12.4 Hardware Multiplier Ope...
  - 12.4.1 Accessing the Multipl...
- 12.5 Hardware Multiplier Per...
- 12.6 Hardware Multiplier Exa...
SECTION 13: 1-Wire BUS MASTER
- 13.1 1-Wire Peripheral Regis...
  - 13.1.1 1-Wire Address Regist...
  - 13.1.2 1-Wire Data Register ...
- 13.2 1-Wire Clock Control
  - 13.2.1 1-Wire Clock Divisor ...
- 13.3 1-Wire Bus Master Control
  - 13.3.1 1-Wire Control Regist...
- 13.4 1-Wire Bus Master Comma...
  - 13.4.1 1-Wire Command Regist...
- 13.5 Search Operation Using ...
  - 13.5.1 Accelerated ROM Searc...
- 13.6 1-Wire Transmit and Rec...
  - 13.6.1 1-Wire Transmit/Recei...
- 13.7 1-Wire Bus Master Inter...
  - 13.7.1 1-Wire Interrupt Flag...
  - 13.7.2 1-Wire Interrupt Enab...
- 13.8 I/O Signaling
SECTION 14: REAL-TIME CLOCK MODULE
- 14.1 RTC Alarm Functions
- 14.2 RTC Trim Function
- 14.3 RTC Register Access
- 14.4 RTC Peripheral Registers
SECTION 15: TEST ACCESS PORT (TAP)
- 15.1 TAP Controller
- 15.2 TAP State Control
- 15.3 Communication via TAP
  - 15.3.1 TAP Communication Exa...
SECTION 16: IN-CIRCUIT DEBUG MODE
- 16.1 Background Mode Operation
  - 16.1.1 Breakpoint Registers
  - 16.1.2 Using Breakpoints
- 16.2 Debug Mode
- 16.3 In-Circuit Debug Periph...
SECTION 17: IN-SYSTEM PROGRAMMING (JTAG)
- 17.1 JTAG Bootloader Operation
- 17.2 Password-Protected Access
  - 17.2.1 Entering Password
SECTION 18: MAXQ FAMILY INSTRUCTION SET SUMMARY
- ADD/ADDC src
- AND src
- AND Acc.
- {L/S}CALL src
- CMP src
- CPL
- CPL C
- {L/S}DJNZ LC[n], src
- {L/S} JUMP src
- {L/S}JUMP C/{L/S}JUMP NC, sr...
- MOVE dst, src
- MOVE Acc., C
- MOVE C, Acc.
- MOVE C, src.
- MOVE C, #0
- MOVE C, #1
- MOVE dst., #0
- MOVE dst., #1
- NEG
- OR src
- OR Acc.
- POP dst
- POPI dst
- PUSH src
- RET
- RET C/RET NC, RET Z/RET NZ, ...
- RETI
- RETI C/RETI NC, RETI Z/RETI ...
- RL/RLC
- RR/RRC
- SLA/SLA2/SLA4
- SR/SRA/SRA2/SRA4
- SUB/SUBB src
- XCH
- XCHN
- XOR src
- XOR Acc.
REVISION HISTORY

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