Maxim Integrated MAXQ Family - Manual (Page 116)

11-4
MAXQ Family User’s Guide
11.3 SPI Transfer Baud Rates
When operating as a slave device, an external master drives the SPI serial clock. For proper slave operation, the serial clock provid-
ed by the external master should not exceed the system clock frequency divided by 8.
When operating in the master mode, the SPI serial clock is sourced to the external slave device(s). The serial clock baud rate is deter-
mined by the clock-divide ratio specified in the SPI Clock Divider Ratio (SPICK) register. The SPI module supports 256 different clock-
divide ratio selections for serial clock generation. The SPICK clock rate is determined by the following formula:
SPI Baud Rate = System Clock Frequency / (2 x Clock Divider Ratio)
where Clock Divider Ratio = (SPICK.7:0) + 1
Since the SPI baud rate is a function of the System Clock Frequency, using any of the system clock divide modes (including Power
Management Mode) alters the baud rate. Attempts to invoke the Power Management Mode while an SPI transfer in is progress (STBY = 1)
are ignored.
Note, however, that once in Power Management Mode (PMME = 1), writes to SPIB in master mode and assertion of the SSEL pin in
slave mode both qualify as switchback sources if enabled (SWB = 1). The SPI module clocks are halted if the device is placed into
Stop mode.
11.4 SPI System Errors
The SPI module can detect three types of SPI system errors. A mode fault error arises in a multiple master system when more than one
SPI device simultaneously tries to be a master. A receive overrun error occurs when an SPI transfer completes before the previous
character has been read from the receive-holding buffer. The third kind of error, write collision, indicates that an attempted write to SPIB
was detected while a transfer was in progress (STBY = 1).
11.4.1 Mode Fault
When a SPI device is configured as a master and its Mode Fault Enable bit (SPICN.2: MODFE) is also set, a mode fault error occurs if
SSEL input signal is driven low by an external device. This error is typically caused when a second SPI device attempts to function as
a master in the system. In the condition where more than one device is configured as master concurrently, there is possibility of bus
contention that can cause permanent damage to push-pull CMOS drivers. The mode fault error detection is to provide protection from
such damage by disabling the bus drivers. When a mode fault is detected, the following actions are taken immediately:
1) The MSTM bit is forced to logic 0 to reconfigure the SPI device as a slave.
2) The SPIEN bit is forced to logic 0 to disable the SPI module.
3) The Mode Fault (SPICN.3: MODF) status flag is set. Setting the MODF bit can generate an interrupt if it is enabled.
The application software must correct the system conflict before resuming its normal operation. The MODF flag is set automatically by
hardware but must be cleared by software or a reset once set. Setting the MODF bit to logic 1 by software causes an interrupt if enabled.
Mode fault detection is optional and can be disabled by clearing the MODFE bit to logic 0. Disabling the mode fault detection disables
the function of the SSEL signal during master mode operation, allowing the associated port pin to be used as a general-purpose I/O.
Note that the mode fault mechanism does not provide full protection from bus contention in multiple master, multiple slave systems.
For example, if two devices are configured as master at the same time, the mode fault-detect circuitry offers protection only when one
of them selects the other as slave by asserting its SSEL signal. Also, if a master accidentally activates more than one slave and those
devices try to simultaneously drive their output pins, bus contention can occur without and a mode fault error being generated.
11.4.2 Receive Overrun
Since the receive direction of SPI is double buffered, there is no overrun condition as long as the received character in the read buffer
is read before the next character in the shift register ready to be transferred to the read buffer. However, if previous data in the read
buffer has not been read out when a transfer cycle is completed and the new character is loaded into the read buffer, a receive over-
run occurs and the Receive Overrun flag (SPICN.5: ROVR) is set. Setting the ROVR flag indicates that the oldest received character
has been overwritten and is lost. Setting the ROVR bit to logic 1 causes an interrupt if enabled. Once set, the ROVR bit is cleared only
by software or a reset.
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