Maxim Integrated MAXQ Family - Manual (Page 146)

14.3 RTC Register Access
Since RTC registers and register bits must be used in the 32kHz clock domain and also be accessible in the system clock domain, a
handshaking or signaling protocol is implemented to simplify user access.
14.3.1 Busy Bit Write Signaling
The BUSY bit of the RTC Control (RCNT) register is a read-only status bit. Hardware sets the BUSY bit when any of the following con-
ditions occur: 1) system reset; 2) software changes the state of any the following RTC bits (RTCE, ASE, ADE); 3) software writes to any
RTC count register (RTSS, RTSL, RTSH). When the BUSY bit is set by hardware, writes to the referenced RTC control bits and count
registers are blocked by hardware. The BUSY bit remains active until a synchronized 32kHz version of the register (or bit) is in place.
This takes place when the next rising edge of the 32kHz clock occurs, which means that the BUSY bit is set for a duration no longer
than one 32kHz clock = ~30.5µs. Once the BUSY bit is cleared to 0, additional writes can be performed as permitted by individual
count or alarm-enable bits.
14.3.2 Ready Bit Read Signaling
The Ready (RDY) bit of the RTC Control (RCNT) register provides a mechanism for determining when the RTC count registers are stable
and may be reliably read. The RDY bit is cleared by hardware approximately one 32kHz clock before the ripple occurs through the RTC
counter chain (RTSS, RTSL, RTSH) and is set once again immediately after the ripple occurs. The period of the RDY bit set/clear activity
(as controlled by hardware) is therefore 1/256Hz = 3.9ms, providing a very large window during which the RTC count registers may be
read. The RDY bit can be cleared by software at any time and remains clear until set by hardware again. A separate Ready Enable (RDYE)
bit is provided in the RCNT register for the purpose of generating an interrupt whenever the RDY bit is set by hardware. This interrupt can
be used to signal the start of a new RTC read window. When RDYE is set to a 1 and RDY becomes set, an interrupt request is generated
if enabled globally and modularly. When RDYE is cleared to 0, the setting of the RDY bit does not generate an interrupt.
14.3.3 RTC Count Register Access
The RTC Count registers (RTSS, RTSL, RTSH) should only be read when RDY = 1. Data read from these registers when RDY = 0 should
be considered as invalid. To write the RTC count registers, the RTC Enable (RTCE) bit must be cleared to 0. Clearing of the RTCE bit
is permitted only when the Write Enable (WE) bit is set to 1 and is governed by the BUSY bit signaling process (i.e., the BUSY bit is
deasserted once a synchronized 32kHz version of the bit is in place). Writes to each RTC count register should also obey the rules
associated with BUSY bit signaling.
14.3.4 RTC Alarm Register Access
The RTC Alarm registers (RSSA, RASL, RASH) are read-accessible at any time. To write the RTC alarm register, the respective alarm
enable (ASE or ADE) bit must be cleared to 0. Clearing these bits requires monitoring the BUSY bit to assess completion of the write.
Once the respective alarm enable is cleared, the associated RTC alarm register(s) can be freely written by user code.
14.3.5 RTC Trim Register Access
These RTC Trim bits (TSGN, TRM4:0) are read-accessible at any time. Write access to these bits requires that the Write Enable (WE)
bit be set to logic 1 and is governed by the BUSY bit signaling process.
14-5
MAXQ Family User’s Guide
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