Maxim Integrated MAXQ Family - Manual (Page 54)

4-8
MAXQ Family User’s Guide
4.14 Stack Pointer Register (SP, Dh[1h])
Bits defined below for 16-word stack depth.
Initialization: This register is cleared to 000Fh on all forms of reset.
Access: Unrestricted direct read/write access.
4.15 Interrupt Vector Register (IV, Dh[2h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
4.16 Loop Counter 0 Register (LC[0], Dh[6h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
4.17 Loop Counter 1 Register (LC[1], Dh[7h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
4.18 Frame Pointer Offset Register (OFFS, Eh[3h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
BIT FUNCTION
SP.3 to SP.0
These four bits indicate the current top of the hardware stack, from 0h to Fh. This pointer is incremented after a value is
pushed on the stack and decremented before a value is popped from the stack.
SP.15 to SP.4 Reserved; all reads return 0.
BIT FUNCTION
IV.15 – IV.0
This register contains the address of the interrupt service routine. The interrupt handler will generate a CALL to this address
whenever an interrupt is acknowledged.
BIT FUNCTION
LC[0].15 to LC[0].0
This register is used as the loop counter for the DJNZ LC[0], src operation. This operation decrements LC[0] by one and then
jumps to the address specified in the instruction by src.
BIT FUNCTION
LC[1].15 to LC[1].0
This register is used as the loop counter for the DJNZ LC[1], src operation. This operation decrements LC[1] by one and
then jumps to the address specified in the instruction by src.
BIT FUNCTION
OFFS.7 to OFFS.0
This 8-bit register provides the Frame Pointer (FP) offset from the base pointer (BP). The Frame Pointer is formed by
unsigned addition of Frame Pointer Base Register (BP) and Frame Pointer Offset Register (Offs). The contents of this
register can be post-incremented or post-decremented when using the Frame Pointer for read operations and may be pre-
incremented or pre-decremented when using the Frame Pointer for write operations. A carry out or borrow resulting from an
increment/decrement operation has no effect on the Frame Pointer Base Register (BP).
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