Maxq family user’s guide – Maxim Integrated MAXQ Family User Manual

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MAXQ Family User’s Guide

SECTION 2: ARCHITECTURE

The MAXQ architecture is designed to be modular and expandable. Top-level instruction decoding is extremely simple and based on

transfers to and from registers. The registers are organized into functional modules, which are in turn divided into the System Register

and Peripheral Register groups. Figure 2-1 illustrates the modular architecture and the basic transport possibilities.

SYSTEM MODULES/

REGISTERS

PERIPHERAL MODULES/REGISTERS

DATA

MEMORY

dst

MAXQ PRODUCT SPECIFIC

MODULES

(MULTIPLY ACCUMULATE UNIT,

ADC, DAC, PWM, ETC.)

STACK

MEMORY

CKCN

WDCN

ADDRESS

GENERATION

LOOP COUNTERS

LC[

η]

IIR

IMR

INTERRUPT

LOGIC

CLOCK CONTROL,

WATCHDOG TIMER

AND POWER MONITOR

BOOLEAN

VARIABLE

MANIPULATION

ACCUMULATORS

(16)

APC

PSF

INSTRUCTION

DECODE

(SRC, DST TRANSPORT

DETERMINATION)

MUX

DATA POINTERS

DP[0], DP[1]

FP =

(BP + OFFS)

DPC

MEMORY MANAGEMENT

UNIT (MMU)

PROGRAM

MEMORY

src

dst

src

GENERAL-

PURPOSE

I/O

TIMERS/

COUNTERS

UART

AND SPI

Figure 2-1. MAXQ Transport-Triggered Architecture

Maxim Integrated