Maxim Integrated MAXQ Family - Manual (Page 173)

16.3.4 In-Circuit Debug Flag Register (ICDF)
Bits 7 to 4: Reserved
Bits 3 to 2: Programming Source Select Bits 1:0 (PSS[1:0]). These bits are used to select a programming interface during In-System
programming when SPE is set to logic 1. Otherwise, the logic values of these bits have no meaning. The logical states of these bits,
when read by the CPU, reflect the logical-OR of the PSS bits that are write accessible by the CPU and those in the System Programming
Buffer (SPB) register of the TAP module (which are accessible via JTAG). These bits are read/write accessible for the CPU and are
cleared to 0 by a power-on reset or Test-Logic-Reset. CPU writes to the PSS bits result in clearing of the JTAG PSS[1:0] bits.
Bit 1: System Program Enable (SPE). The SPE bit is used for in-system programming support and its logical state, when by the CPU,
always reflects the logical-OR of the SPE bit that is write accessible by the CPU and SPR bit of the System Programming Buffer (SPB)
Register in the TAP Module (which is accessible via JTAG.) The logical state of this bit determines the program flow after a reset. When
it is set to logic 1, in-system programming is executed by the Utility ROM. When it is cleared to 0, execution is transferred to user code.
This but allows read/write access by the SPU and is cleared to 0 only on a power-on reset or Test-Logic-Reset. The JTAG SPE bit is
cleared by hardware when the ROD bit is set. CPU writes to the SPE bit result in clearing the JTAG PSS[1:0] bits.
Bit 0: Serial Transfer Complete (TXC). This bit is set by hardware at the end of a transfer cycle at the TAP communication link. The
TXC bit helps the debug engine to recognize host requests, either command or data. This bit is normally set by ROM code to signify
or request the sending or receiving of data. The TXC bit is cleared by the debug engine once set. CPU writes to the TXC bit results in
clearing of the JTAG PSS[1:0] bits.
16.3.5 In-Circuit Debug Buffer Register (ICDB)
Bits 7 to 0: In-Circuit Debug Buffer Register (ICDB.[7:0]). This register serves as the parallel holding buffer for the debug shift reg-
ister of the TAP. Data is read from or written to ICDB for serial communication between the debug routines and the external host.
16-15
MAXQ Family User’s Guide
Bit # 7 6 5 4 3 2 1 0
Name — — — — PSS1 PSS0 SPE TXC
Reset 0 0 0 0 0 0 0 0
Access r r r r rw rw rw rw
r = read, w = write
PSS1 PSS0 SOURCE SELECTION
0 0 JTAG
0 1 UART
1 0 SPI
1 1 Reserved
Bit # 7 6 5 4 3 2 1 0
Name ICDB.7 ICDB.6 ICDB.5 ICDB.4 ICDB.3 ICDB.2 ICDB.1 ICDB.0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
r = read, w = write
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