Maxim Integrated MAXQ Family - Manual (Page 144)

14.1 RTC Alarm Functions
The RTC provides time-of-day and sub-second interval alarm functions. The time-of-day alarm, when enabled, occurs based upon
matching of the least significant 20 bits of the RTC seconds counter information (RTSH:RTSL) with the least significant 20 bits of the
alarm register values (RASH:RASL) defined by the user. The sub-second interval alarm provides an auto-reload timer that is driven by
the untrimmed 256Hz clock source.
14.1.1 Time-of-Day Alarm
The RTC Alarm Second High and RTC Alarm Second Low registers (RASH and RASL) provide a programmable, 20-bit time-of-day
alarm function. The 20 bits of the time-of-day alarm should be programmed with the desired value to match with the least significant
20 bits of the RTC seconds counter for the purpose of triggering an alarm. The least significant 16 bits of the time-of-day alarm are
programmable in the RASL register, while the most significant 4 bits of the alarm value are programmable in the lowest 4 bits of the
RASH register. The time-of-day alarm can be programmed to any future value between 1 second and 12 days relative to the current
time with a resolution of 1 second. The time-of-day alarm must be disabled before the changing the time-of-day alarm registers. The
time-of-day alarm is a single event alarm that sets the ALDF flag to 1 when an RTSS rollover occurs and the contents of RTSH and
RTSL counter registers match the 20-bit value set in the RASH and RASL alarm registers. Setting the ALDF bit causes an interrupt
request to the processor if the ADE bit and the system interrupt enable are set.
14.1.2 Sub-Second Alarm
The RTC Sub-Second Alarm (RSSA) register is used to store the sub-second interval alarm value for the sub-second alarm function.
The RSSA register is independent of the RTC counter value and is configurable per MAXQ device as necessary to 16 bits to achieve
sub-second interval alarms needed by various applications. The default RSSA register size is 8 bits wide, allowing a maximum inter-
val alarm of 1 second and a programming resolution of ~3.9 milliseconds (1/256Hz). The sub-second interval alarm must be disabled
(ASE = 0 and BUSY = 0) before changing the interval alarm value.
The delay (uncertainty) associated with the enabling of the interval sub-second alarm is up to one period of the sub-second clock
(1/256Hz = ~3.9ms). Thus, the same uncertainty is associated with the first interval alarm. Thereafter, if the interval alarm remains
enabled, the alarm triggers after each RSSA defined sub-second interval. This is due to the fact that the sub-second alarm is con-
structed as an auto-reload counter such that the RSSA alarm value is reloaded to the counter only on a rollover. Note that enabling the
sub-second alarm (ASE = 1) with sub-second interval alarm register programmed to 0's results in the maximum sub-second alarm
interval (1 second if RSSA = 8 bits wide).
The sub-second interval counter sources its clock from the 32kHz/128 counter before the possible insertion of pulses by the digital-
trim facility. This is done to keep the alarm interval consistent and avoid deviations in the interval that would automatically be created
each time the digital-trim facility were to add/subtract clock pulses.
14.1.3 System Wakeup by Time-of-Day or Sub-Second Interval Alarm
The time-of-day alarm or interval alarm can wake up the system from Stop mode if not already awake. The wakeup function is allowed
only when these interrupts have not been masked at all levels. The time-of-day and interval alarms also qualify as valid Power
Management Mode switchback sources.
14.2 RTC Trim Function
The uncompensated accuracy of the RTC is a function of the attached crystal (and its respective temperature drift characteristics with-
in the end system). To accommodate those applications requiring high accuracy, a digital-trim facility is made accessible to the user.
The trim facility allows extra clocks to be inserted or removed at the 256Hz stage of the divider chain. Five trim bits (TRM4:0) are used
to control the trim adjustment, and the sign bit (TSGN) designates whether pulses should be inserted (TSGN = 0) or deleted
(TSGN = 1). Every 16 seconds, the five trim bits are added to the previous phase accumulator value. Whenever the phase accumula-
tor generates a carry-out from the addition, the output of the 512Hz stage is selected instead of the 256Hz stage if positive trim is
selected, effectively adding 128 extra 32kHz clocks. If negative trim is selected, the 256Hz stage output pulse is masked in order to
effectively subtract 128 32kHz clocks. The 512Hz or 1Hz output can be made accessible on an external pin as controlled by the FT
and SQE bits. Figure 14-2 shows a block diagram illustrating the digital-trim facility. Figure 14-3 shows a representative timing diagram.
The minimum adjustment (00001h) would result in a phase accumulator carry-out every 32 x 16 seconds = 512 seconds or adding/sub-
tracting 1 pulse (=128 cycles of 32.768kHz) every 512 seconds. This would be an adjustment of 128 / (32,768Hz x 512s) = ±7.63ppm.
The maximum adjustment would be achieved by programming TRM4:0 = 11111b. This would result in an adjustment of 31 extra puls-
es per 512-second interval or (31 x 128) / (32,768Hz x 512s) = ±236.5ppm. This range of adjustment should be satisfactory to cover
the temperature drift characteristics of most 32kHz crystals over the industrial temperature range.
14-3
MAXQ Family User’s Guide
Maxim Integrated