Maxim Integrated MAXQ Family - Manual (Page 95)

9-17
MAXQ Family User’s Guide
Compare Mode:
If SS2 is written to 1 while in compare mode, one cycle of the defined waveform (reload to overflow) is output to the T2P, T2PB pins as
prescribed by T2POL[1:0] and T2OE[1:0] controls. The only time that this does not immediately occur is when a gating condition is
also defined. If a gating condition is defined, the single-shot cycle cannot occur until the gating condition is removed. If the specified
non-gated level is already in effect, the singleshot period will start. The gated single-shot output is not supported in dual 8-bit mode.
Capture Mode:
If SS2 is written to 1 while in capture mode, the timer is halted and the single-shot capture cycle does not begin until the edge speci-
fied by CCF[1:0] is detected, or the defined gating condition is removed. Once running, the timer continues running (as allowed by the
gate condition) until the defined capture single-shot edge is detected. In this way, the SS2 bit can be used to delay the running of a
timer until an edge is detected (setting both SS2 and TR2 =1) or override the TR2 = 0 bit setting for one capture cycle (setting only
SS2 = 1). When both edges are defined for capture CCF[1:0] = 11b), the T2POL[0] bit serves to define the single-shot start/end edge:
falling edge if T2POL[0] = 1; rising edge if T2POL[0] = 0. No interrupt flag is set when the starting edge for the single-shot capture
cycle is detected. The single-shot capture cycle always ends when the next single shot edge is detected. The start/end edge is defined
by T2POL[0]. This bit is intended to automate pulse-width measurement (low or high) and duty cycle/period measurement.
Bit 0: Gating Enable (G2EN). This bit enables the external T2P pin to gate the input clock to the 16-bit (T2MD = 0) or highest 8-bit
(T2MD = 1) Timer. Gating uses T2P as an input, thus it can only be used when T2OE0 = 0 and C/T2 = 0. Gating is not possible on the
low 8-bit timer (T2L) when Timer 2 is operated in dual 8-bit mode. Gating is not supported for counter mode operation (C/T2 = 1). The
G2EN bit serves a different purpose when capture and reload have been defined for both edges (CCF[1:0] = 11b and CPRL2 = 1).
For this special case, setting G2EN = 1 allows the T2POL0 bit to specify which edge does not cause a reload. If T2POL0 is 0, no reload
on the falling edge; if T2POL0 is 1, no reload on the rising edge.
0 = gating disabled
1 = gating enabled
9.4.3 Timer/Counter 2 Control Register B (T2CNB)
Bit 7: Enable Timer 2 Low Interrupts (ET2L). This bit serves as the local enable for Timer 2 Low interrupt sources that fall under the
TF2L and TC2L interrupt flags.
Bit 6: Timer 2 Output Enable 1 (T2OE1). See table given under T2CNA.5 description. The T2OE1 bit is not implemented for single
pin versions of Timer 2.
Bit 5: Timer 2 Polarity Select 1 (T2POL1). When the T2B output is enabled (T2OE1 = 1), this bit selects the starting logic level for the
alternate pin output. The output that is driven on the T2PB pin can be derived from the 16-bit Timer 2 or the 8-Timer (T2L) depending
upon whether operating in the 16-bit mode or the dual 8-bit mode. The T2POL1 bit can be modified anytime, but takes effect on the
external pin when T2OE1 is changed from 0 to 1.
Bit 3: Timer 2 Overflow Flag (TF2). This flag becomes set anytime there is an overflow of the full 16-bit T2V timer/counter (when T2MD
= 0) or an overflow of the 8-bit T2H timer/counter when the dual 8-bit mode of operation is selected (T2MD = 1).
Bit 2: Timer 2 Low Overflow Flag (TF2L). This flag is meaningful only when in the dual 8-bit mode of operation (T2MD = 1) and
becomes set whenever there is an overflow of the T2L 8-bit timer.
Bit 1: Timer 2 Capture/Compare Flag (TCC2). This flag is set on any compare match between the Timer 2 value and compare reg-
ister (T2V = T2C or T2H = T2CH, respectively, for 16-bit and 8-bit compare modes) or when a capture event is initiated by an external
edge.
Bit 0: Timer 2 Low Compare Flag (TC2L). This flag is meaningful only for the dual 8-bit mode of operation (T2MD = 1) and becomes
set only when a compare match occurs between T2CL and T2L. Timer 2 Low does not have an associated capture function.
Bit # 7 6 5 4 3 2 1 0
Name ET2L T2OE1 T2POL1 — TF2 TF2L TCC2 TC2L
Reset 0 0 0 0 0 0 0 0
Access rw rw rw r rw rw rw rw
r = read, w = write
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