Maxim Integrated MAXQ Family - Manual (Page 167)

16-9
MAXQ Family User’s Guide
16.1.2 Using Breakpoints
All breakpoint registers (BP0-BP5) default to the FFFFh state on power-on reset or when the Test-Logic-Reset TAP state is entered. The
breakpoint registers are accessible only with Background mode read/write commands issued over the TAP communication link. The
breakpoint registers are not read/write accessible to the CPU.
Setting the Debug Mode Enable (DME) bit in the ICDC register to logic 1 enables all six breakpoint registers for breakpoint match com-
parison. The state of the Break-On Register Enable (REGE) bit in the ICDC register determines whether the BP4 and BP5 breakpoints
should be used as data memory address breakpoints (REGE = 0) or as register breakpoints (REGE = 1).
When using the register matching breakpoints, it is important to realize that Debug mode operations (e.g., read data memory, write
data memory, etc.) require use of ICDA and ICDD for passing of information between the host and MAXQ microcontroller ROM rou-
tines. It is advised that these registers be saved and restored or be reconfigured before returning to the background mode if register
breakpoints are to remain enabled.
When a breakpoint match occurs, the debug engine forces a break and the MAXQ microcontroller enters Debug Mode. If a breakpoint
match occurs on an instruction that activates the PFX register, the break is held off until the prefixed operation completes. The host can
assess whether Debug mode has been entered by monitoring the status bits of the 10-bit word shifted out of the TDO pin. The status
bits will change from the Non-debug (00b) state associated with background mode to the Debug-Idle (01b) state when Debug Mode
is entered. Debug mode can also be manually invoked by host issuance of the 'Debug' background command.
16.2 Debug Mode
There are two ways to enter the Debug Mode from Background Mode:
• Issuance of the Debug command directly by the host via the TAP communication port, or
• Breakpoint matching mechanism.
The host can issue the Debug background command to the debug engine. This direct Debug Mode entry is indeterministic. The
response time varies dependent on system conditions when the command is issued. The breakpoint mechanism provides a more con-
trollable response, but requires that the breakpoints be initially configured in Background mode. No matter the method of entry, the
debug engine takes control of the CPU in the same manner. Debug mode entry is similar to the state machine flow of an interrupt except
that the target execution address is x8010h which resides in the Utility ROM instead of the address specified by the IV register that is
used for interrupts. On debug mode entry, the following actions occur:
1) block the next instruction fetch from program memory
2) push the return address onto the stack
3) set the contents of IP to x8010h
4) clear the IGE bit to 0 to disable interrupt handler if it is not already clear.
5) halt CPU operation
Once in Debug mode, further breakpoint matches or host issuance of the Debug command are treated as no operations and will not
disturb debug engine operation. Entering debug mode also stops the clocks to all timers, including the Watchdog Timer. Temporarily
disabling these functions allows debug mode operations without disrupting the relationship between the original user program code
and hardware timed functions. No interrupt request can be granted since the interrupt handler is also halted as a result of IGE = 0.
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