Maxim Integrated MAXQ Family - Manual (Page 111)

10.4 UART Peripheral Registers
10.4.1 Serial Control Register (SCON)
Bit 7: Framing Error Flag (FE). (FEDE = 1) This bit is set upon detection of an invalid stop bit. It must be cleared by software.
Modification of this bit when FEDE is set has no effect on the serial mode setting.
Bit 7: Serial Port 0 Mode Bit 0 (SM0). (FEDE = 0) This bit is used in conjunction with the SM2 and SM1 bits to define the serial mode.
Bit 6: Serial Port 0 Mode Bit 1 (SM1). See the above table for more information.
Bit 5: Serial Port 0 Mode Bit 2 (SM2). Setting this bit in mode 1 ignores reception if an invalid stop bit is detected. Setting this bit in
mode 2 or 3 enables multiprocessor communications, and prevents the RI bit from being set and the interrupt from being asserted if
the 9th bit received is 0. See the above table for more information. This bit is also used to support mode 0 for clock selection:
0 = serial clock is system clock divided by 12
1 = serial clock is system clock divided by 4
Bit 4: Receive Enable (REN)
0 = serial port receiver disabled
1 = serial port receiver enabled for modes 1, 2, and 3; initiate synchronous reception for mode 0 (if RI = 0)
Bit 3: 9th Transmission Bit State (TB8). This bit defines the state of the 9th transmission bit in serial port modes 2 and 3.
Bit 2: 9th Received Bit State (RB8). This bit identifies the state of the 9th bit of received data in serial port modes 2 and 3. When SM2
is 0, it is the state of the stop bit in mode 1. This bit has no meaning in mode 0.
Bit 1: Transmit Interrupt Flag (TI). This bit indicates that the data in the serial port data buffer has been completely shifted out. It is
set at the end of the last data bit for all modes of operation and must be cleared by software once set.
Bit 0: Receive Interrupt Flag (RI). This bit indicates that a data byte has been received in the serial port buffer. The bit is set at the
end of the 8th bit for mode 0, after the last sample of the incoming stop bit for mode 1 subject to the value of the SM2 bit, or after the
last sample of RB8 for modes 2 and 3. This bit must be cleared by software once set.
10-10
MAXQ Family User’s Guide
Bit # 7 6 5 4 3 2 1 0
Name FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
r = read, w = write
MODE SM[2:0] FUNCTION LENGTH PERIOD
0 0 0 0 Synchronous 8 Bits 12 System Clock
0 1 0 0 Synchronous 8 Bits 4 System Clock
1 x 1 0 Asynchronous 10 Bits 64/16 Baud Clock (SMOD = 0/1)
2 0 0 1 Asynchronous 11 Bits 64/32 System Clock (SMOD = 0/1)
2 1 0 1 Asynchronous (MP) 11 Bits 64/32 System Clock (SMOD = 0/1)
3 0 1 1 Asynchronous 11 Bits 64/16 Baud Clock (SMOD = 0/1)
3 1 1 1 Asynchronous (MP) 11 Bits 64/16 Baud Clock (SMOD = 0/1)
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