Maxim Integrated MAXQ Family - Manual (Page 50)

4-4
MAXQ Family User’s Guide
4.6 System Control Register (SC, 8h[8h])
Initialization: This register is reset to 100000s0b on all reset. Bit 1 (PWL) is set to 1 on a power-on reset only.
Access: Unrestricted read/write access.
4.7 Interrupt Identification Register (IIR, 8h[Bh])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Read only.
BIT FUNCTION
SC.0 Reserved. All reads return 0.
SC.1 (PWL)
Password Lock. This bit defaults to 1 on a power-on reset. When this bit is 1, it requires a 32-byte password to be matched with
the password in the program space before allowing access to the password protected in-circuit debug or bootstrap loader
ROM routines. Clearing this bit to 0 disables the password protection for these ROM routines.
SC.2 (ROD)
ROM Operation Done. This bit is used to signify completion of a ROM operation sequence to the control units. This allows the
Debug engine to determine the status of a ROM sequence. Setting this bit to logic 1 causes an internal system reset if the JTAG
SPE bit is also set. Setting the ROD bit will clear the JTAG SPE bit if it is set and the ROD bit will be automatically cleared by
hardware once the control unit acknowledges the done indication.
SC.3 (UPA)
Upper Program Access. The physical program memory is logically divided into four pages; P0 and P1 occupy the lower
32kWords while P2 and P3 occupy the upper 32kWords. P0 and P1 are assigned to the lower half of the program space and are
always active. P2 and P3 must be explicitly activated in the upper half of the program space by setting the UPA bit to 1. When
UPA bit is cleared to 0, the upper program memory space is occupied by the Utility ROM and the logical data memory, which is
accessible as program memory. Note that the UPA is not implemented if the upper 32K of the program space is not used for the
user code.
Code Data Access Bits 1:0. The CDA bits are used to logically map physical program memory page to the data space for
read/write access:
CDA1:0 BYTE MODE ACTIVE PAGE WORD MODE ACTIVE PAGE
00 P0 P0 and P1
01 P1 P0 and P1
10 P2 P2 and P3
11 P3 P2 and P3
SC.5 and SC.4
(CDA1, CDA0)
The logical data memory addresses of the program pages depend on whether execution is from Utility ROM or logical data
memory. Note that CDA1 is not implemented if the upper 32k of the program space is not used for the user code. No CDA bits
are needed if only one page of program space is incorporated.
SC.6 Reserved. All reads return 0.
SC.7 (TAP)
Test Access (JTAG) Port Enable. This bit controls whether the Test Access Port special-function pins are enabled. The TAP
defaults to being enabled. Clearing this bit to 0 disables the TAP special function pins.
BIT FUNCTION
The first six bits in this register indicate interrupts pending in modules 0 to 5, one bit per module. The eighth bit, IIS, indicates
a pending system interrupt, such as from the watchdog timer. The interrupt pending flags will be set only for enabled interrupt
sources waiting for service. The interrupt pending flag will be cleared when the pending interrupt sources within that module
are disabled or when the interrupt flags are cleared by software
IIR.0 (II0) Interrupt Identifier Flag for Register Module 0
IIR.1 (II1) Interrupt Identifier Flag for Register Module 1
IIR.2 (II2) Interrupt Identifier Flag for Register Module 2
IIR.3 (II3) Interrupt Identifier Flag for Register Module 3
IIR.4 (II4) Interrupt Identifier Flag for Register Module 4
IIR.5 (II5) Interrupt Identifier Flag for Register Module 5
IIR.6 Reserved. Reads return 0.
IIR.7 (IIS) Interrupt Identifier Flag for System Modules
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