Maxim Integrated MAXQ Family - Manual (Page 140)

13-11
MAXQ Family User’s Guide
13.7.2 1-Wire Interrupt Enable Register (OWA = 011b)
Bit 7: Enable 1-Wire Low Interrupt (EOWL). Setting this bit to logic 1 enables the 1-Wire low interrupt. If both EOWMI and EOWL are
set, OWMI is asserted when OW_LOW flag is set. Clearing this bit disables OW_LOW as an active interrupt source.
Bit 6: Enable 1-Wire Short Interrupt (EOWSH). Setting this bit to logic 1 enables the 1-Wire short interrupt. If both EOWMI and
EOWSH are set, OWMI is asserted when OW_SHORT flag is set. Clearing this bit disables OW_SHORT as an active interrupt source.
Bit 5: Enable Receive Shift Register Full Interrupt (ERSF). Setting this bit to logic 1 enables the receive shift register full interrupt.
If both EOWMI and ERSF are set, OWMI is asserted when RSRF flag is set. Clearing this bit disables RSRF as an active interrupt source.
Bit 4: Enable Receive Buffer Full Interrupt (ERBF). Setting this bit to logic 1 enables the receive buffer full interrupt. If both EOWMI
and ERBF are set, OWMI is asserted when RBF flag is set. Clearing this bit disables RBF as an active interrupt source.
Bit 3: Enable Transmit Shift Register Empty Interrupt (ETMT). Setting this bit to logic 1 enables the transmit shift register empty
interrupt. If both EOWMI and ETMT are set, OWMI is asserted when TEMT flag is set. Clearing this bit disables TEMT as an active inter-
rupt source.
Bit 2: Enable Transmit Buffer Empty Interrupt (ETBE). Setting this bit to logic 1 enables the transmit buffer empty interrupt. If both
EOWMI and ETBE are set, OWMI is asserted when TBE flag is set. Clearing this bit disables TBE as an active interrupt source.
Bit 1: Reserved
Bit 0: Enable Presence Detect Interrupt (EPD). Setting this bit to a logic 1 enables the presence detect interrupt. If both EOWMI and
EPD are set, OWMI will be asserted after an appropriate amount of time has passed for a presence-detect pulse to have occurred,
whenever a 1-Wire Reset is sent while the presence-detect flag (PD) is also set. Clearing this bit disables the presence detect as an
active interrupt source.
13.8 I/O Signaling
The 1-Wire bus requires strict signaling protocols to ensure integrity. The five protocols used by the 1-Wire Bus Master are initialization
sequence (Reset Pulse followed by Presence Pulse), Write 0, Write 1, Read 0, and Read 1. The Bus Master initiates all of these types
of signaling except the presence pulse. Figure 13-2 illustrates the details of these signaling protocols.
The initialization sequence is required to begin any communication with the bus slave devices. The 1-Wire Bus Master transmits a reset
pulse for t RSTL . The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the rising edge on the OWOUT pin, the
slave device waits for t PDH and then transmits the Presence Pulse for t PDL . A Presence Pulse following a Reset Pulse indicates the
slave device is ready to accept a ROM command. The Bus Master samples the bus at tPDS after the slave device responds to test for
a valid presence pulse. The result of this sample is stored in the PDR bit of the Interrupt Flag Register. The reset time slot ends tRSTH
after the Bus Master releases the bus.
A write time slot is initiated when the 1-Wire Bus Master pulls the 1-Wire bus line from a logic high (inactive) level to a logic low level.
The Bus Master generates a Write 1 time slot by releasing the line at t LOW1 and allowing the line to pullup to logic high level. On the
other hand, the line is held low for t LOW0 to generate a Write 0 time slot. A slave device samples the 1-Wire bus line between 15µs and
60µs after the line falls. If the line is high when sampled, a Write 1 occurs. If the line is low when sampled, a Write 0 occurs.
A read time slot is initiated when the 1-Wire Master pulls the bus low for at least 1(s and then releases it. The slave device continues
to hold the line low for up to 60µs if it is responding with a 0, otherwise it releases it immediately. The Bus Master samples the data
t RDV from the start of the read time slot. If the line is high when sampled, a Read 1 occurs. If the line is low when sampled, a Read 0
occurs. The Bus Master ends the read slot after t SLOT .
Bit # 7 6 5 4 3 2 1 0
Name EOWL EOWSH ERSF ERBF ETMT ETBE — EPD
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw r rw
r = read, w = write
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