Maxim Integrated MAXQ Family - Manual (Page 39)

3-14
MAXQ Family User’s Guide
Once the interrupt handler receives the interrupt, the Interrupt in Service (INS) bit will be set by hardware to block further interrupts,
and execution control is transferred to the interrupt service routine. Within the interrupt service routine, the source of the interrupt must
be determined. Since all interrupts go to the same interrupt service routine, the Interrupt Identification Register (IIR) must be examined
to determine which module initiated the interrupt. For example, the II0 (IIR.0) bit will be set if there is a pending interrupt from module
0. These bits cannot be cleared directly; instead, the appropriate bit flag in the module must be cleared once the interrupt is handled.
INS is set automatically on entry to the interrupt handler and cleared automatically on exit (RETI).
IntHandler:
push PSF ; save C since used in identification process
move C, IIR.X ; check highest priority flag in IIR
jump C, ISR_X ; if IIR.X is set, interrupt from module X
move C, IIR.Y ; check next highest priority int source
jump C, ISR_Y ; if IIR.Y is set, interrupt from module Y
...
ISR_X:
...
reti
To support high priority interrupts while servicing another interrupt source, the IMR register may be used to create a user-defined prior-
itization. The IMR mask register should not be utilized when the highest priority interrupt is being serviced because the highest priority
interrupt should never be interrupted. This is default condition when a hardware branch is made the Interrupt Vector address (INS is set
to 1 by hardware and all other interrupt sources are blocked). The code below demonstrates how to use IMR to allow other interrupts.
ISR_Z:
pop PSF ; restore PSF
push IMR ; save current interrupt mask
move IMR, #int_mask ; new mask to allow only higher priority ints
move INS, #0 ; re-enable interrupts
...
(interrupt servicing code)
...
pop IMR ; restore previous interrupt mask
ret ; back to code or lower priority interrupt
Please note that configuring a given IMR register mask bit to '0' only prevents interrupt conditions from the corresponding module or sys-
tem from generating an interrupt request. Configuring an IMR mask bit to '0' does not prevent the corresponding IIR system or module iden-
tification flag from being set. This means that when using the IMR mask register functionality to block interrupts, there may be cases when
both the mask (IMR.x) and identifier (IIR.x) bits should be considered when determining if the corresponding peripheral should be serviced.
3.8.1 Conditional Return from Interrupt
Similar to the conditional returns, the MAXQ microcontroller also supports a set of conditional return from interrupt operations. Based
upon the value of one of the status flags, the CPU can conditionally pop the stack, clear the INS bit to 0, and begin execution at the
address popped from the stack. If the condition is not true, the conditional return from interrupt instruction leaves the INS bit
unchanged, does not pop the stack and does not change the instruction pointer. The following conditional return from interrupt oper-
ations are supported:
RETI C ; if C=1, a RETI is executed
RETI NC ; if C=0, a RETI is executed
RETI Z ; if Z=1 (Acc=00h), a RETI is executed
RETI NZ ; if Z=0 (Acc<>00h), a RETI is executed
RETI S ; if S=1, a RETI is executed
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