Maxim Integrated MAXQ Family - Manual (Page 171)

allows user code to configure breakpoints that occur inside PMM, thus providing reliable use of debug commands. However, it does
not allow a good means for re-entering PMM.
• Special caution should be exercised when using the Write Register command on register bits that globally affect system operation
(e.g., IGE, STOP). If the write register command is used to invoke stop mode (setting STOP = 1), the RST pin may be asserted to
reset the debug engine and return to the background mode of operation.
• Single stepping ('Trace') through any IGE bit change operation results in the debug engine overriding the bit change since it retains
the IGE bit setting captured when active debug mode was entered.
• Single stepping ('Trace') into an operation that sets STOP = 1 when IGE = 1 effectively allows enabled interrupts normally capable
of causing exit from stop mode to do so.
• Single stepping ('Trace') through any memory read instruction that reads from the utility ROM (such as 'move Acc,' @DP[0] with
DP[0] set to 8000h) will cause the memory read to return an incorrect value.
• Single stepping ('Trace') cannot be used when executing code from the utility ROM.
• Data memory allocation is important during system development if in-circuit debug is planned. The top 32-byte memory location
may be used by the debug service routine during debug mode. The data contents in these locations may be altered and cannot be
recovered.
• One available stack location is needed for debug mode. If the stack is full when entering debug mode, the oldest data in the stack
will be overwritten.
• The crystal warmup counter is the only counter not disabled when active debug mode is entered. If the crystal warmup counter com-
pletes while in active debug mode, a glitchless switch will be made to selected clock source (which was being counted). It is impor-
tant that the user recognize that this action will occur since the TAP clock should be run no faster than 1/8 the system clock frequency.
• Any signal sampling that relies upon the internal system clock (e.g., counter inputs) can be unreliable since the system clock is
turned off inside active debug mode between debug mode commands.
• Power Management Mode cannot be invoked in the first instruction executed when returning from active debug mode. The PMME
bit will not be set if such an attempt is made.
16.3 In-Circuit Debug Peripheral Registers
16.3.1 In-Circuit Debug Temp 0 Register (ICDT0)
Bits 15 to 0: In-Circuit Debug Temp 0 (ICDT0.[15:0]). This register is read/write accessible by the CPU only in background mode or
debug mode. This register is intended for use by the utility ROM routines as temporary storage to save registers that might otherwise
have to be placed in the stack.
16-13
MAXQ Family User’s Guide
Bit # 15 14 13 12 11 10 9 8
Name ICDT0.15 ICDT0.14 ICDT0.13 ICDT0.12 ICDT0.11 ICDT0.10 ICDT0.9 ICDT0.8
Reset 0 0 0 0 0 0 0 0
Access s s s s s s s s
Bit # 7 6 5 4 3 2 1 0
Name ICDT0.7 ICDT0.6 ICDT0.5 ICDT0.4 ICDT0.3 ICDT0.2 ICDT0.1 ICDT0.0
Reset 0 0 0 0 0 0 0 0
Access s s s s s s s s
s = special
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